Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 2 | /* |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 3 | * Copyright (C) 2021 Tony Dinh <mibodhi@gmail.com> |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 4 | * (C) Copyright 2011 |
| 5 | * Jason Cooper <u-boot@lakedaemon.net> |
| 6 | * |
| 7 | * Based on work by: |
| 8 | * Marvell Semiconductor <www.marvell.com> |
| 9 | * Written-by: Siddarth Gore <gores@marvell.com> |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 13 | #include <init.h> |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 14 | #include <miiphy.h> |
Simon Glass | 0c36441 | 2019-12-28 10:44:48 -0700 | [diff] [blame] | 15 | #include <net.h> |
Anatolij Gustschin | cc94214 | 2011-10-29 11:19:47 +0000 | [diff] [blame] | 16 | #include <asm/arch/cpu.h> |
Stefan Roese | c243784 | 2014-10-22 12:13:06 +0200 | [diff] [blame] | 17 | #include <asm/arch/soc.h> |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 18 | #include <asm/arch/mpp.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 19 | #include <asm/global_data.h> |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 20 | #include "dreamplug.h" |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | int board_early_init_f(void) |
| 25 | { |
| 26 | /* |
| 27 | * default gpio configuration |
| 28 | * There are maximum 64 gpios controlled through 2 sets of registers |
| 29 | * the below configuration configures mainly initial LED status |
| 30 | */ |
Stefan Roese | c50ab39 | 2014-10-22 12:13:11 +0200 | [diff] [blame] | 31 | mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW, |
| 32 | DREAMPLUG_OE_VAL_HIGH, |
| 33 | DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 34 | |
| 35 | /* Multi-Purpose Pins Functionality configuration */ |
Albert ARIBAUD | 4d42431 | 2012-11-26 11:27:36 +0000 | [diff] [blame] | 36 | static const u32 kwmpp_config[] = { |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 37 | MPP0_SPI_SCn, /* SPI Flash */ |
| 38 | MPP1_SPI_MOSI, |
| 39 | MPP2_SPI_SCK, |
| 40 | MPP3_SPI_MISO, |
| 41 | MPP4_NF_IO6, |
| 42 | MPP5_NF_IO7, |
| 43 | MPP6_SYSRST_OUTn, |
| 44 | MPP7_GPO, |
| 45 | MPP8_TW_SDA, |
| 46 | MPP9_TW_SCK, |
| 47 | MPP10_UART0_TXD, /* Serial */ |
| 48 | MPP11_UART0_RXD, |
| 49 | MPP12_SD_CLK, /* SDIO Slot */ |
| 50 | MPP13_SD_CMD, |
| 51 | MPP14_SD_D0, |
| 52 | MPP15_SD_D1, |
| 53 | MPP16_SD_D2, |
| 54 | MPP17_SD_D3, |
| 55 | MPP18_NF_IO0, |
| 56 | MPP19_NF_IO1, |
| 57 | MPP20_GE1_0, /* Gigabit Ethernet */ |
| 58 | MPP21_GE1_1, |
| 59 | MPP22_GE1_2, |
| 60 | MPP23_GE1_3, |
| 61 | MPP24_GE1_4, |
| 62 | MPP25_GE1_5, |
| 63 | MPP26_GE1_6, |
| 64 | MPP27_GE1_7, |
| 65 | MPP28_GE1_8, |
| 66 | MPP29_GE1_9, |
| 67 | MPP30_GE1_10, |
| 68 | MPP31_GE1_11, |
| 69 | MPP32_GE1_12, |
| 70 | MPP33_GE1_13, |
| 71 | MPP34_GE1_14, |
| 72 | MPP35_GE1_15, |
| 73 | MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */ |
| 74 | MPP37_GPIO, |
| 75 | MPP38_GPIO, |
| 76 | MPP39_GPIO, |
| 77 | MPP40_TDM_SPI_SCK, |
| 78 | MPP41_TDM_SPI_MISO, |
| 79 | MPP42_TDM_SPI_MOSI, |
| 80 | MPP43_GPIO, |
| 81 | MPP44_GPIO, |
| 82 | MPP45_GPIO, |
| 83 | MPP46_GPIO, |
| 84 | MPP47_GPIO, /* Bluetooth LED */ |
| 85 | MPP48_GPIO, /* Wifi LED */ |
| 86 | MPP49_GPIO, /* Wifi AP LED */ |
| 87 | 0 |
| 88 | }; |
Valentin Longchamp | 7d0d502 | 2012-06-01 01:31:00 +0000 | [diff] [blame] | 89 | kirkwood_mpp_conf(kwmpp_config, NULL); |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 90 | return 0; |
| 91 | } |
| 92 | |
| 93 | int board_init(void) |
| 94 | { |
| 95 | /* adress of boot parameters */ |
Stefan Roese | 0b74175 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 96 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 101 | static int fdt_get_phy_addr(const char *path) |
| 102 | { |
| 103 | const void *fdt = gd->fdt_blob; |
| 104 | const u32 *reg; |
| 105 | const u32 *val; |
| 106 | int node, phandle, addr; |
| 107 | |
| 108 | /* Find the node by its full path */ |
| 109 | node = fdt_path_offset(fdt, path); |
| 110 | if (node >= 0) { |
| 111 | /* Look up phy-handle */ |
| 112 | val = fdt_getprop(fdt, node, "phy-handle", NULL); |
| 113 | if (val) { |
| 114 | phandle = fdt32_to_cpu(*val); |
| 115 | if (!phandle) |
| 116 | return -1; |
| 117 | /* Follow it to its node */ |
| 118 | node = fdt_node_offset_by_phandle(fdt, phandle); |
| 119 | if (node) { |
| 120 | /* Look up reg */ |
| 121 | reg = fdt_getprop(fdt, node, "reg", NULL); |
| 122 | if (reg) { |
| 123 | addr = fdt32_to_cpu(*reg); |
| 124 | return addr; |
| 125 | } |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | return -1; |
| 130 | } |
| 131 | |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 132 | #ifdef CONFIG_RESET_PHY_R |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 133 | void mv_phy_88e1116_init(const char *name, const char *path) |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 134 | { |
| 135 | u16 reg; |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 136 | int phyaddr; |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 137 | |
| 138 | if (miiphy_set_current_dev(name)) |
| 139 | return; |
| 140 | |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 141 | phyaddr = fdt_get_phy_addr(path); |
| 142 | if (phyaddr < 0) |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 143 | return; |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * Enable RGMII delay on Tx and Rx for CPU port |
| 147 | * Ref: sec 4.7.2 of chip datasheet |
| 148 | */ |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 149 | miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); |
| 150 | miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL2_REG, ®); |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 151 | reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 152 | miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL2_REG, reg); |
| 153 | miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 154 | |
| 155 | /* reset the phy */ |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 156 | miiphy_reset(name, phyaddr); |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 157 | |
| 158 | printf("88E1116 Initialized on %s\n", name); |
| 159 | } |
| 160 | |
| 161 | void reset_phy(void) |
| 162 | { |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 163 | char *eth0_name = "ethernet-controller@72000"; |
| 164 | char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0"; |
| 165 | char *eth1_name = "ethernet-controller@76000"; |
Tony Dinh | ed2416d | 2021-09-06 16:28:35 -0700 | [diff] [blame] | 166 | char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0"; |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 167 | |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 168 | /* configure and initialize both PHY's */ |
Tony Dinh | 4cd9477 | 2021-07-25 23:01:19 -0700 | [diff] [blame] | 169 | mv_phy_88e1116_init(eth0_name, eth0_path); |
| 170 | mv_phy_88e1116_init(eth1_name, eth1_path); |
Jason Cooper | 8d038fa | 2011-10-03 13:49:53 +0530 | [diff] [blame] | 171 | } |
| 172 | #endif /* CONFIG_RESET_PHY_R */ |