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Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +09001/*
2 * Configuation settings for the ESPT-GIGA board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +09008 */
9
10#ifndef __ESPT_H
11#define __ESPT_H
12
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090013#define CONFIG_CPU_SH7763 1
14#define CONFIG_ESPT 1
15#define __LITTLE_ENDIAN 1
16
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090017#define CONFIG_ENV_OVERWRITE 1
18
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020019#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090020#undef CONFIG_SHOW_BOOT_PROGRESS
21
22/* SCIF */
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090023#define CONFIG_CONS_SCIF0 1
24
Nobuhiro Iwamatsu62662012011-01-17 21:15:44 +090025#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090026#define CONFIG_SYS_LONGHELP /* undef to save memory */
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090027#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090028#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
29 settings for this board */
30
31/* SDRAM */
32#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
33#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
34#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
35#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
36
37/* Flash(NOR) S29JL064H */
38#define CONFIG_SYS_FLASH_BASE (0xA0000000)
39#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
40#define CONFIG_SYS_MAX_FLASH_BANKS (1)
41#define CONFIG_SYS_MAX_FLASH_SECT (150)
42
Bin Meng75574052016-02-05 19:30:11 -080043/* U-Boot setting */
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090044#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
45#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
46#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
47/* Size of DRAM reserved for malloc() use */
48#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090049#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
50
51#define CONFIG_SYS_FLASH_CFI
52#define CONFIG_FLASH_CFI_DRIVER
53#undef CONFIG_SYS_FLASH_QUIET_TEST
54#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
55/* Timeout for Flash erase operations (in ms) */
56#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
57/* Timeout for Flash write operations (in ms) */
58#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
59/* Timeout for Flash set sector lock bit operations (in ms) */
60#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
61/* Timeout for Flash clear lock bit operations (in ms) */
62#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
63/* Use hardware flash sectors protection instead of U-Boot software protection */
64#undef CONFIG_SYS_FLASH_PROTECTION
65#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090066#define CONFIG_ENV_SECT_SIZE (128 * 1024)
67#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
68#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
69/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
70#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
71#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
72#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
73
74/* Clock */
75#define CONFIG_SYS_CLK_FREQ 66666666
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090076#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
77#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090078#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090079
80/* Ether */
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090081#define CONFIG_SH_ETHER 1
82#define CONFIG_SH_ETHER_USE_PORT (1)
83#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
Yoshihiro Shimoda6a49bb52011-10-31 10:44:19 +090084#define CONFIG_BITBANGMII
85#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsu32f900e2012-05-16 10:23:21 +090086#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Nobuhiro Iwamatsud1f2a0c2009-06-25 16:31:26 +090087
88#endif /* __SH7763RDP_H */