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Christophe Kerello9dc34792019-04-05 11:41:49 +02001STMicroelectronics Flexible Memory Controller 2 (FMC2)
2NAND Interface
3
4Required properties:
5- compatible: Should be one of:
6 * st,stm32mp15-fmc2
7- reg: NAND flash controller memory areas.
8 First region contains the register location.
9 Regions 2 to 4 respectively contain the data, command,
10 and address space for CS0.
11 Regions 5 to 7 contain the same areas for CS1.
12- interrupts: The interrupt number
13- pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
14- clocks: The clock needed by the NAND flash controller
15
16Optional properties:
17- resets: Reference to a reset controller asserting the FMC controller
18- dmas: DMA specifiers (see: dma/stm32-mdma.txt)
19- dma-names: Must be "tx", "rx" and "ecc"
20
21Optional children nodes:
22Children nodes represent the available NAND chips.
23
24Optional properties:
25- nand-on-flash-bbt: see nand.txt
26- nand-ecc-strength: see nand.txt
27- nand-ecc-step-size: see nand.txt
28
29The following ECC strength and step size are currently supported:
30 - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
31 - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
32 - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default)
33
34Example:
35
36 fmc: nand-controller@58002000 {
37 compatible = "st,stm32mp15-fmc2";
38 reg = <0x58002000 0x1000>,
39 <0x80000000 0x1000>,
40 <0x88010000 0x1000>,
41 <0x88020000 0x1000>,
42 <0x81000000 0x1000>,
43 <0x89010000 0x1000>,
44 <0x89020000 0x1000>;
45 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
46 clocks = <&rcc FMC_K>;
47 resets = <&rcc FMC_R>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&fmc_pins_a>;
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 nand@0 {
54 reg = <0>;
55 nand-on-flash-bbt;
56 #address-cells = <1>;
57 #size-cells = <1>;
58 };
59 };