Tom Rini | 8b0c8a1 | 2018-05-06 18:27:01 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _MACH_STM32_H_ |
| 7 | #define _MACH_STM32_H_ |
| 8 | |
| 9 | /* |
| 10 | * Peripheral memory map |
| 11 | * only address used before device tree parsing |
| 12 | */ |
| 13 | #define STM32_RCC_BASE 0x50000000 |
| 14 | #define STM32_PWR_BASE 0x50001000 |
| 15 | #define STM32_DBGMCU_BASE 0x50081000 |
| 16 | #define STM32_TZC_BASE 0x5C006000 |
| 17 | #define STM32_ETZPC_BASE 0x5C007000 |
Patrick Delaunay | 82b88ef | 2019-07-05 17:20:11 +0200 | [diff] [blame] | 18 | #define STM32_STGEN_BASE 0x5C008000 |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 19 | #define STM32_TAMP_BASE 0x5C00A000 |
| 20 | |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 21 | #define STM32_USART1_BASE 0x5C000000 |
| 22 | #define STM32_USART2_BASE 0x4000E000 |
| 23 | #define STM32_USART3_BASE 0x4000F000 |
| 24 | #define STM32_UART4_BASE 0x40010000 |
| 25 | #define STM32_UART5_BASE 0x40011000 |
| 26 | #define STM32_USART6_BASE 0x44003000 |
| 27 | #define STM32_UART7_BASE 0x40018000 |
| 28 | #define STM32_UART8_BASE 0x40019000 |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 29 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 30 | #define STM32_SYSRAM_BASE 0x2FFC0000 |
| 31 | #define STM32_SYSRAM_SIZE SZ_256K |
| 32 | |
| 33 | #define STM32_DDR_BASE 0xC0000000 |
| 34 | #define STM32_DDR_SIZE SZ_1G |
| 35 | |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 36 | #ifndef __ASSEMBLY__ |
Patrick Delaunay | 089d435 | 2018-03-20 11:45:14 +0100 | [diff] [blame] | 37 | /* enumerated used to identify the SYSCON driver instance */ |
| 38 | enum { |
| 39 | STM32MP_SYSCON_UNKNOWN, |
Patrick Delaunay | aa78531 | 2018-04-26 16:45:18 +0200 | [diff] [blame] | 40 | STM32MP_SYSCON_PWR, |
Patrick Delaunay | 63ae49e | 2019-02-27 17:01:23 +0100 | [diff] [blame] | 41 | STM32MP_SYSCON_SYSCFG, |
Patrick Delaunay | 089d435 | 2018-03-20 11:45:14 +0100 | [diff] [blame] | 42 | }; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT |
| 46 | * - boot device = bit 8:4 |
| 47 | * - boot instance = bit 3:0 |
| 48 | */ |
| 49 | #define BOOT_TYPE_MASK 0xF0 |
| 50 | #define BOOT_TYPE_SHIFT 4 |
| 51 | #define BOOT_INSTANCE_MASK 0x0F |
| 52 | #define BOOT_INSTANCE_SHIFT 0 |
| 53 | |
| 54 | enum boot_device { |
| 55 | BOOT_FLASH_SD = 0x10, |
| 56 | BOOT_FLASH_SD_1 = 0x11, |
| 57 | BOOT_FLASH_SD_2 = 0x12, |
| 58 | BOOT_FLASH_SD_3 = 0x13, |
| 59 | |
| 60 | BOOT_FLASH_EMMC = 0x20, |
| 61 | BOOT_FLASH_EMMC_1 = 0x21, |
| 62 | BOOT_FLASH_EMMC_2 = 0x22, |
| 63 | BOOT_FLASH_EMMC_3 = 0x23, |
| 64 | |
| 65 | BOOT_FLASH_NAND = 0x30, |
| 66 | BOOT_FLASH_NAND_FMC = 0x31, |
| 67 | |
| 68 | BOOT_FLASH_NOR = 0x40, |
| 69 | BOOT_FLASH_NOR_QSPI = 0x41, |
| 70 | |
| 71 | BOOT_SERIAL_UART = 0x50, |
| 72 | BOOT_SERIAL_UART_1 = 0x51, |
| 73 | BOOT_SERIAL_UART_2 = 0x52, |
| 74 | BOOT_SERIAL_UART_3 = 0x53, |
| 75 | BOOT_SERIAL_UART_4 = 0x54, |
| 76 | BOOT_SERIAL_UART_5 = 0x55, |
| 77 | BOOT_SERIAL_UART_6 = 0x56, |
| 78 | BOOT_SERIAL_UART_7 = 0x57, |
| 79 | BOOT_SERIAL_UART_8 = 0x58, |
| 80 | |
| 81 | BOOT_SERIAL_USB = 0x60, |
| 82 | BOOT_SERIAL_USB_OTG = 0x62, |
| 83 | }; |
| 84 | |
| 85 | /* TAMP registers */ |
| 86 | #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) |
Patrick Delaunay | e020737 | 2018-04-16 10:13:24 +0200 | [diff] [blame] | 87 | #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) |
| 88 | #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) |
Fabien Dessenne | d7700d1 | 2019-10-30 14:38:29 +0100 | [diff] [blame] | 89 | #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) |
| 90 | #define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 91 | #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) |
Patrick Delaunay | 9c07f4a | 2019-04-18 17:32:45 +0200 | [diff] [blame] | 92 | #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 93 | |
Fabien Dessenne | d7700d1 | 2019-10-30 14:38:29 +0100 | [diff] [blame] | 94 | #define TAMP_COPRO_STATE_OFF 0 |
| 95 | #define TAMP_COPRO_STATE_INIT 1 |
| 96 | #define TAMP_COPRO_STATE_CRUN 2 |
| 97 | #define TAMP_COPRO_STATE_CSTOP 3 |
| 98 | #define TAMP_COPRO_STATE_STANDBY 4 |
| 99 | #define TAMP_COPRO_STATE_CRASH 5 |
| 100 | |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 101 | #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) |
| 102 | #define TAMP_BOOT_MODE_SHIFT 8 |
| 103 | #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) |
| 104 | #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 105 | #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) |
Patrick Delaunay | bff284f | 2019-07-30 19:16:20 +0200 | [diff] [blame] | 106 | #define TAMP_BOOT_DEBUG_ON BIT(16) |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 107 | |
| 108 | enum forced_boot_mode { |
| 109 | BOOT_NORMAL = 0x00, |
| 110 | BOOT_FASTBOOT = 0x01, |
| 111 | BOOT_RECOVERY = 0x02, |
| 112 | BOOT_STM32PROG = 0x03, |
| 113 | BOOT_UMS_MMC0 = 0x10, |
| 114 | BOOT_UMS_MMC1 = 0x11, |
| 115 | BOOT_UMS_MMC2 = 0x12, |
| 116 | }; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 117 | |
Patrick Delaunay | 14d6a24 | 2018-05-17 15:24:05 +0200 | [diff] [blame] | 118 | /* offset used for BSEC driver: misc_read and misc_write */ |
| 119 | #define STM32_BSEC_SHADOW_OFFSET 0x0 |
Patrick Delaunay | 92dc102 | 2019-02-12 11:44:41 +0100 | [diff] [blame] | 120 | #define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4) |
Patrick Delaunay | 14d6a24 | 2018-05-17 15:24:05 +0200 | [diff] [blame] | 121 | #define STM32_BSEC_OTP_OFFSET 0x80000000 |
Patrick Delaunay | 92dc102 | 2019-02-12 11:44:41 +0100 | [diff] [blame] | 122 | #define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4) |
| 123 | |
| 124 | #define BSEC_OTP_BOARD 59 |
Patrick Delaunay | 14d6a24 | 2018-05-17 15:24:05 +0200 | [diff] [blame] | 125 | |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 126 | #endif /* __ASSEMBLY__*/ |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 127 | #endif /* _MACH_STM32_H_ */ |