| Daniel Schwierzeck | e4ccb47 | 2020-07-12 01:46:18 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 MIPS Tech, LLC |
| 4 | * Author: Matt Redfearn <matt.redfearn@mips.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __MIPS_ASM_ISA_REV_H__ |
| 8 | #define __MIPS_ASM_ISA_REV_H__ |
| 9 | |
| 10 | /* |
| 11 | * The ISA revision level. This is 0 for MIPS I to V and N for |
| 12 | * MIPS{32,64}rN. |
| 13 | */ |
| 14 | |
| 15 | /* If the compiler has defined __mips_isa_rev, believe it. */ |
| 16 | #ifdef __mips_isa_rev |
| 17 | #define MIPS_ISA_REV __mips_isa_rev |
| 18 | #else |
| 19 | /* The compiler hasn't defined the isa rev so assume it's MIPS I - V (0) */ |
| 20 | #define MIPS_ISA_REV 0 |
| 21 | #endif |
| 22 | |
| 23 | |
| 24 | #endif /* __MIPS_ASM_ISA_REV_H__ */ |