| Ralph Siemsen | 9446dfe | 2023-05-12 21:36:56 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Device Tree Source for Schneider RZ/N1 Board |
| 4 | * |
| 5 | * Based on r9a06g032-rzn1d400-db.dts |
| 6 | */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | |
| 10 | #include <dt-bindings/pinctrl/rzn1-pinctrl.h> |
| 11 | #include "r9a06g032.dtsi" |
| 12 | |
| 13 | / { |
| 14 | model = "Schneider RZ/N1 Board"; |
| 15 | compatible = "schneider,rzn1", "renesas,r9a06g032"; |
| 16 | |
| 17 | chosen { |
| 18 | stdout-path = "serial0:115200n8"; |
| 19 | }; |
| 20 | |
| 21 | aliases { |
| 22 | serial0 = &uart0; |
| 23 | }; |
| 24 | |
| 25 | memory { |
| 26 | device_type = "memory"; |
| 27 | reg = <0x80000000 0x10000000>; |
| 28 | }; |
| 29 | |
| 30 | soc { |
| 31 | plat_regs: syscon@4000c000 { |
| 32 | compatible = "syscon"; |
| 33 | reg = <0x4000c000 0x1000>; |
| 34 | }; |
| 35 | |
| 36 | system-controller@4000c000 { |
| 37 | regmap = <&plat_regs>; |
| 38 | }; |
| 39 | |
| 40 | ddrctrl: memory-controller@4000d000 { |
| 41 | compatible = "cadence,ddr-ctrl"; |
| 42 | reg = <0x4000d000 0x1000>, <0x4000e000 0x100>; |
| 43 | reg-names = "ddrc", "phy"; |
| 44 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 45 | clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl R9A06G032_HCLK_DDRC>; |
| 46 | clock-names = "clk_ddrc", "hclk_ddrc"; |
| 47 | syscon = <&plat_regs>; |
| 48 | status = "disabled"; |
| 49 | }; |
| 50 | }; |
| 51 | |
| 52 | reboot { |
| 53 | compatible = "syscon-reboot"; |
| 54 | regmap = <&plat_regs>; |
| 55 | offset = <0x198>; /* sysctrl.RSTEN */ |
| 56 | mask = <0x40>; /* bit 6 = SWRST_REQ */ |
| 57 | value = <0x40>; |
| 58 | }; |
| 59 | }; |
| 60 | |
| 61 | &ddrctrl { |
| 62 | status = "okay"; |
| 63 | |
| 64 | conf-1 { |
| 65 | size = <0x40000000>; /* 1 GB */ |
| 66 | #include "renesas/is43tr16256a_125k_CTL.h" |
| 67 | #include "r9a06g032-ddr.dtsi" |
| 68 | }; |
| 69 | conf-2 { |
| 70 | size = <0x10000000>; /* 256 MB */ |
| 71 | #include "renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h" |
| 72 | #include "r9a06g032-ddr.dtsi" |
| 73 | }; |
| 74 | }; |
| 75 | |
| 76 | &pinctrl { |
| 77 | status = "okay"; |
| 78 | |
| 79 | pins_uart0: pins_uart0 { |
| 80 | pinmux = < |
| 81 | RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ |
| 82 | RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ |
| 83 | >; |
| 84 | bias-disable; |
| 85 | }; |
| 86 | }; |
| 87 | |
| 88 | &uart0 { |
| 89 | pinctrl-0 = <&pins_uart0>; |
| 90 | pinctrl-names = "default"; |
| 91 | status = "okay"; |
| 92 | }; |