blob: 4d12440fa3c0cec918ccb1dfdfa44c0a044d9dc8 [file] [log] [blame]
Daniel Gollef8c29bf2023-04-11 17:19:46 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7986.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "BananaPi BPi-R3";
15 compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb";
16
17 chosen {
18 stdout-path = &uart0;
19 tick-timer = &timer0;
20 };
21
22 reg_3p3v: regulator-3p3v {
23 compatible = "regulator-fixed";
24 regulator-name = "fixed-3.3V";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 regulator-boot-on;
28 regulator-always-on;
29 };
30
31 keys {
32 compatible = "gpio-keys";
33
34 factory {
35 label = "reset";
36 gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
37 };
38
39 wps {
40 label = "wps";
41 gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
42 };
43 };
44
45 leds {
46 compatible = "gpio-leds";
47
48 led_status_green: green {
49 label = "green:status";
50 gpios = <&gpio 69 GPIO_ACTIVE_HIGH>;
51 };
52
53 led_status_blue: blue {
54 label = "blue:status";
55 gpios = <&gpio 86 GPIO_ACTIVE_HIGH>;
56 };
57 };
58
59};
60
61&uart0 {
62 status = "okay";
63};
64
65&uart1 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&uart1_pins>;
68 status = "disabled";
69};
70
71&eth {
72 status = "okay";
73 mediatek,gmac-id = <0>;
74 phy-mode = "sgmii";
75 mediatek,switch = "mt7531";
76 reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
77
78 fixed-link {
79 speed = <1000>;
80 full-duplex;
81 };
82};
83
84&pinctrl {
85 spic_pins: spi1-pins-func-1 {
86 mux {
87 function = "spi";
88 groups = "spi1_2";
89 };
90 };
91
92 uart1_pins: spi1-pins-func-3 {
93 mux {
94 function = "uart";
95 groups = "uart1_2";
96 };
97 };
98
99 pwm_pins: pwm0-pins-func-1 {
100 mux {
101 function = "pwm";
102 groups = "pwm0";
103 };
104 };
105
106 mmc0_pins_default: mmc0default {
107 mux {
108 function = "flash";
109 groups = "emmc_51";
110 };
111
112 conf-cmd-dat {
113 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
114 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
115 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
116 input-enable;
117 drive-strength = <MTK_DRIVE_4mA>;
118 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
119 };
120
121 conf-clk {
122 pins = "EMMC_CK";
123 drive-strength = <MTK_DRIVE_6mA>;
124 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
125 };
126
127 conf-dsl {
128 pins = "EMMC_DSL";
129 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
130 };
131
132 conf-rst {
133 pins = "EMMC_RSTB";
134 drive-strength = <MTK_DRIVE_4mA>;
135 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
136 };
137 };
138
139 spi_flash_pins: spi0-pins-func-1 {
140 mux {
141 function = "flash";
142 groups = "spi0", "spi0_wp_hold";
143 };
144
145 conf-pu {
146 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
147 drive-strength = <MTK_DRIVE_8mA>;
148 bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
149 };
150
151 conf-pd {
152 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
153 drive-strength = <MTK_DRIVE_8mA>;
154 bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
155 };
156 };
157};
158
159&pwm {
160 pinctrl-names = "default";
161 pinctrl-0 = <&pwm_pins>;
162 status = "okay";
163};
164
165&spi0 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&spi_flash_pins>;
170 status = "okay";
171 must_tx;
172 enhance_timing;
173 dma_ext;
174 ipm_design;
175 support_quad;
176 tick_dly = <1>;
177 sample_sel = <0>;
178
179 spi_nor@0 {
180 compatible = "jedec,spi-nor";
181 reg = <0>;
182 spi-max-frequency = <52000000>;
183
184 partitions {
185 compatible = "fixed-partitions";
186 #address-cells = <1>;
187 #size-cells = <1>;
188
189 partition@0 {
190 label = "bl2";
191 reg = <0x0 0x40000>;
192 };
193
194 partition@40000 {
195 label = "u-boot-env";
196 reg = <0x40000 0x40000>;
197 };
198
199 partition@80000 {
200 label = "reserved";
201 reg = <0x80000 0x80000>;
202 };
203
204 partition@100000 {
205 label = "fip";
206 reg = <0x100000 0x80000>;
207 };
208
209 partition@180000 {
210 label = "recovery";
211 reg = <0x180000 0xa80000>;
212 };
213
214 partition@c00000 {
215 label = "fit";
216 reg = <0xc00000 0x1400000>;
217 };
218 };
219 };
220
221 spi_nand@1 {
222 compatible = "spi-nand";
223 reg = <1>;
224 spi-max-frequency = <52000000>;
225
226 partitions {
227 compatible = "fixed-partitions";
228 #address-cells = <1>;
229 #size-cells = <1>;
230
231 partition@0 {
232 label = "bl2";
233 reg = <0x0 0x80000>;
234 };
235
236 partition@80000 {
237 label = "factory";
238 reg = <0x80000 0x300000>;
239 };
240
241 partition@380000 {
242 label = "fip";
243 reg = <0x380000 0x200000>;
244 };
245
246 partition@580000 {
247 label = "ubi";
248 reg = <0x580000 0x7a80000>;
249 };
250 };
251 };
252};
253
254&watchdog {
255 status = "disabled";
256};
257
258&mmc0 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&mmc0_pins_default>;
261 bus-width = <4>;
262 max-frequency = <52000000>;
263 cap-sd-highspeed;
264 r_smpl = <1>;
265 vmmc-supply = <&reg_3p3v>;
266 vqmmc-supply = <&reg_3p3v>;
267 status = "okay";
268};