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git01.mediatek.com / filogic / uboot / e17596d0db84c272690fc72b3667ffe142544cbb / . / arch / arm / dts / imx8mn-var-som.dtsi
blob: 4eb578a03fcbce3a0bcc73f3524355ff165f210a [file] [log] [blame]
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright 2019-2020 Variscite Ltd.
5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
6 */
7
8#include "imx8mn.dtsi"
9
10/ {
11 model = "Variscite VAR-SOM-MX8MN module";
12 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
13
Hugo Villeneuved3cdac42023-05-25 17:02:25 -0400[diff] [blame]14 aliases {
15 eeprom-som = &eeprom_som;
16 };
17
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]18 chosen {
19 stdout-path = &uart4;
20 };
21
22 memory@40000000 {
23 device_type = "memory";
24 reg = <0x0 0x40000000 0 0x40000000>;
25 };
26
27 reg_eth_phy: regulator-eth-phy {
28 compatible = "regulator-fixed";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_reg_eth_phy>;
31 regulator-name = "eth_phy_pwr";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
35 enable-active-high;
36 };
37};
38
39&A53_0 {
40 cpu-supply = <&buck2_reg>;
41};
42
43&A53_1 {
44 cpu-supply = <&buck2_reg>;
45};
46
47&A53_2 {
48 cpu-supply = <&buck2_reg>;
49};
50
51&A53_3 {
52 cpu-supply = <&buck2_reg>;
53};
54
55&ecspi1 {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_ecspi1>;
58 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
59 <&gpio1 0 GPIO_ACTIVE_LOW>;
60 /delete-property/ dmas;
61 /delete-property/ dma-names;
62 status = "okay";
63
64 /* Resistive touch controller */
65 touchscreen@0 {
66 reg = <0>;
67 compatible = "ti,ads7846";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_restouch>;
70 interrupt-parent = <&gpio1>;
71 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
72
73 spi-max-frequency = <1500000>;
74 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
75
76 ti,x-min = /bits/ 16 <125>;
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]77 touchscreen-size-x = <4008>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]78 ti,y-min = /bits/ 16 <282>;
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]79 touchscreen-size-y = <3864>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]80 ti,x-plate-ohms = /bits/ 16 <180>;
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]81 touchscreen-max-pressure = <255>;
82 touchscreen-average-samples = <10>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]83 ti,debounce-tol = /bits/ 16 <3>;
84 ti,debounce-rep = /bits/ 16 <1>;
85 ti,settle-delay-usec = /bits/ 16 <150>;
86 ti,keep-vref-on;
87 wakeup-source;
88 };
89};
90
91&fec1 {
92 pinctrl-names = "default", "sleep";
93 pinctrl-0 = <&pinctrl_fec1>;
94 pinctrl-1 = <&pinctrl_fec1_sleep>;
95 phy-mode = "rgmii";
96 phy-handle = <&ethphy>;
97 phy-supply = <&reg_eth_phy>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]98 fsl,magic-packet;
99 status = "okay";
100
101 mdio {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
Hugo Villeneuvefd8b9f92023-05-25 17:02:27 -0400[diff] [blame]105 ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]106 compatible = "ethernet-phy-ieee802.3-c22";
107 reg = <4>;
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]108 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
109 reset-assert-us = <10000>;
Hugo Villeneuvefd8b9f92023-05-25 17:02:27 -0400[diff] [blame]110 /*
111 * Deassert delay:
112 * ADIN1300 requires 5ms.
113 * AR8033 requires 1ms.
114 */
115 reset-deassert-us = <20000>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]116 };
117 };
118};
119
120&i2c1 {
121 clock-frequency = <400000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_i2c1>;
124 status = "okay";
125
126 pmic@4b {
127 compatible = "rohm,bd71847";
128 reg = <0x4b>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_pmic>;
131 interrupt-parent = <&gpio2>;
132 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
133 rohm,reset-snvs-powered;
134
135 regulators {
136 buck1_reg: BUCK1 {
137 regulator-name = "buck1";
138 regulator-min-microvolt = <700000>;
139 regulator-max-microvolt = <1300000>;
140 regulator-boot-on;
141 regulator-always-on;
142 regulator-ramp-delay = <1250>;
143 };
144
145 buck2_reg: BUCK2 {
146 regulator-name = "buck2";
147 regulator-min-microvolt = <700000>;
148 regulator-max-microvolt = <1300000>;
149 regulator-boot-on;
150 regulator-always-on;
151 regulator-ramp-delay = <1250>;
152 rohm,dvs-run-voltage = <1000000>;
153 rohm,dvs-idle-voltage = <900000>;
154 };
155
156 buck3_reg: BUCK3 {
157 regulator-name = "buck3";
158 regulator-min-microvolt = <700000>;
159 regulator-max-microvolt = <1350000>;
160 regulator-boot-on;
161 regulator-always-on;
162 };
163
164 buck4_reg: BUCK4 {
165 regulator-name = "buck4";
166 regulator-min-microvolt = <2600000>;
167 regulator-max-microvolt = <3300000>;
168 regulator-boot-on;
169 regulator-always-on;
170 };
171
172 buck5_reg: BUCK5 {
173 regulator-name = "buck5";
174 regulator-min-microvolt = <1605000>;
175 regulator-max-microvolt = <1995000>;
176 regulator-boot-on;
177 regulator-always-on;
178 };
179
180 buck6_reg: BUCK6 {
181 regulator-name = "buck6";
182 regulator-min-microvolt = <800000>;
183 regulator-max-microvolt = <1400000>;
184 regulator-boot-on;
185 regulator-always-on;
186 };
187
188 ldo1_reg: LDO1 {
189 regulator-name = "ldo1";
190 regulator-min-microvolt = <1600000>;
191 regulator-max-microvolt = <1900000>;
192 regulator-boot-on;
193 regulator-always-on;
194 };
195
196 ldo2_reg: LDO2 {
197 regulator-name = "ldo2";
198 regulator-min-microvolt = <800000>;
199 regulator-max-microvolt = <900000>;
200 regulator-boot-on;
201 regulator-always-on;
202 };
203
204 ldo3_reg: LDO3 {
205 regulator-name = "ldo3";
206 regulator-min-microvolt = <1800000>;
207 regulator-max-microvolt = <3300000>;
208 regulator-boot-on;
209 regulator-always-on;
210 };
211
212 ldo4_reg: LDO4 {
213 regulator-name = "ldo4";
214 regulator-min-microvolt = <900000>;
215 regulator-max-microvolt = <1800000>;
216 regulator-always-on;
217 };
218
219 ldo5_reg: LDO5 {
220 regulator-compatible = "ldo5";
221 regulator-min-microvolt = <1800000>;
222 regulator-max-microvolt = <1800000>;
223 regulator-always-on;
224 };
225
226 ldo6_reg: LDO6 {
227 regulator-name = "ldo6";
228 regulator-min-microvolt = <900000>;
229 regulator-max-microvolt = <1800000>;
230 regulator-boot-on;
231 regulator-always-on;
232 };
233 };
234 };
Hugo Villeneuved3cdac42023-05-25 17:02:25 -0400[diff] [blame]235
236 eeprom_som: eeprom@52 {
237 compatible = "atmel,24c04";
238 reg = <0x52>;
239 pagesize = <16>;
240 };
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]241};
242
243&i2c3 {
244 clock-frequency = <400000>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c3>;
247 status = "okay";
248
249 /* TODO: configure audio, as of now just put a placeholder */
250 wm8904: codec@1a {
251 compatible = "wlf,wm8904";
252 reg = <0x1a>;
253 status = "disabled";
254 };
255};
256
257&snvs_pwrkey {
258 status = "okay";
259};
260
261/* Bluetooth */
262&uart2 {
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_uart2>;
265 assigned-clocks = <&clk IMX8MN_CLK_UART2>;
266 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
267 uart-has-rtscts;
268 status = "okay";
269};
270
271/* Console */
272&uart4 {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_uart4>;
275 status = "okay";
276};
277
278&usbotg1 {
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]279 dr_mode = "otg";
280 usb-role-switch;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]281 status = "okay";
282};
283
284/* WIFI */
285&usdhc1 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 pinctrl-names = "default", "state_100mhz", "state_200mhz";
289 pinctrl-0 = <&pinctrl_usdhc1>;
290 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
291 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
292 bus-width = <4>;
293 non-removable;
294 keep-power-in-suspend;
295 status = "okay";
296
297 brcmf: bcrmf@1 {
298 reg = <1>;
299 compatible = "brcm,bcm4329-fmac";
300 };
301};
302
303/* SD */
304&usdhc2 {
305 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
306 assigned-clock-rates = <200000000>;
307 pinctrl-names = "default", "state_100mhz", "state_200mhz";
308 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
309 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
310 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
311 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
312 bus-width = <4>;
313 vmmc-supply = <&reg_usdhc2_vmmc>;
314 status = "okay";
315};
316
317/* eMMC */
318&usdhc3 {
319 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
320 assigned-clock-rates = <400000000>;
321 pinctrl-names = "default", "state_100mhz", "state_200mhz";
322 pinctrl-0 = <&pinctrl_usdhc3>;
323 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
324 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
325 bus-width = <8>;
326 non-removable;
327 status = "okay";
328};
329
330&wdog1 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_wdog>;
333 fsl,ext-reset-output;
334 status = "okay";
335};
336
337&iomuxc {
338 pinctrl_ecspi1: ecspi1grp {
339 fsl,pins = <
340 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
341 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
342 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
343 MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
344 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
345 >;
346 };
347
348 pinctrl_fec1: fec1grp {
349 fsl,pins = <
350 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
351 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
352 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
353 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
354 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
355 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
356 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
357 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
358 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
359 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
360 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
361 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
362 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
363 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
364 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
365 >;
366 };
367
368 pinctrl_fec1_sleep: fec1sleepgrp {
369 fsl,pins = <
370 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
371 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
372 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
373 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
374 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
375 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
376 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
377 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
378 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
379 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
380 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
381 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
382 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
383 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
384 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
385 >;
386 };
387
388 pinctrl_i2c1: i2c1grp {
389 fsl,pins = <
390 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
391 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
392 >;
393 };
394
395 pinctrl_i2c3: i2c3grp {
396 fsl,pins = <
397 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
398 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
399 >;
400 };
401
402 pinctrl_pmic: pmicirqgrp {
403 fsl,pins = <
404 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
405 >;
406 };
407
408 pinctrl_reg_eth_phy: regethphygrp {
409 fsl,pins = <
410 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
411 >;
412 };
413
414 pinctrl_restouch: restouchgrp {
415 fsl,pins = <
416 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
417 >;
418 };
419
420 pinctrl_uart2: uart2grp {
421 fsl,pins = <
422 MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
423 MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
424 MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
425 MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
426 >;
427 };
428
429 pinctrl_uart4: uart4grp {
430 fsl,pins = <
431 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
432 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
433 >;
434 };
435
436 pinctrl_usdhc1: usdhc1grp {
437 fsl,pins = <
438 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
439 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
440 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
441 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
442 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
443 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
444 >;
445 };
446
447 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
448 fsl,pins = <
449 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
450 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
451 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
452 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
453 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
454 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
455 >;
456 };
457
458 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
459 fsl,pins = <
460 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
461 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
462 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
463 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
464 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
465 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
466 >;
467 };
468
469 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
470 fsl,pins = <
471 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
472 >;
473 };
474
475 pinctrl_usdhc2: usdhc2grp {
476 fsl,pins = <
477 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
478 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
479 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
480 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
481 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
482 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
483 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
484 >;
485 };
486
487 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
488 fsl,pins = <
489 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
490 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
491 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
492 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
493 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
494 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
495 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
496 >;
497 };
498
499 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
500 fsl,pins = <
501 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
502 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
503 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
504 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
505 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
506 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
507 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
508 >;
509 };
510
511 pinctrl_usdhc3: usdhc3grp {
512 fsl,pins = <
513 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
514 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
515 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
516 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
517 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
518 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
519 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
520 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
521 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
522 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
523 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
524 >;
525 };
526
527 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
528 fsl,pins = <
529 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
530 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
531 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
532 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
533 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
534 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
535 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
536 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
537 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
538 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
539 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
540 >;
541 };
542
543 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
544 fsl,pins = <
545 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
546 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
547 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
548 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
549 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
550 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
551 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
552 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
553 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
554 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
555 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
556 >;
557 };
558
559 pinctrl_wdog: wdoggrp {
560 fsl,pins = <
561 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
562 >;
563 };
564};