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git01.mediatek.com / filogic / uboot / e17596d0db84c272690fc72b3667ffe142544cbb / . / arch / arm / dts / imx8mm-cl-iot-gate-optee-u-boot.dtsi
blob: 484e31824b8573036a7c3b46c38821d1017c5fbf [file] [log] [blame]
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Marcel Ziswiler9888e122021-10-23 01:15:12 +0200[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]8/ {
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]15
16 wdt-reboot {
17 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]19 wdt = <&wdog1>;
20 };
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]21};
22
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]23&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]25};
26
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]27&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]29};
30
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]31&binman_fip {
32 arch = "arm64";
33 compression = "none";
34 description = "Trusted Firmware FIP";
35 load = <0x40310000>;
36 type = "firmware";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]37
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]38 fip_blob {
39 filename = "fip.bin";
40 type = "blob-ext";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]41 };
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]42};
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]43
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]44&binman_configuration {
45 loadables = "atf", "fip";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]46};
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]47
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]48&fec1 {
49 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
50};
51
52&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]54};
55
56&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]58};
59
60&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]62};
63
64&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]66};
67
68&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]70};
71
72&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]74};
75
76&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]78};
79
80&pinctrl_i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]82};
83
84&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]86};
87
88&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]90};
91
92&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]94};
95
96&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]98};
99
100&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]102};
103
104&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]106};
107
108&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]110};
111
112&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]114};
115
116&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]118};
119
120&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]122};