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Michael Walle36ba7642020-10-15 23:08:57 +02001// SPDX-License-Identifier: GPL-2.0+
2
3#include <config.h>
4
5/ {
6 aliases {
Michael Walle36ba7642020-10-15 23:08:57 +02007 i2c0 = &i2c0;
8 i2c1 = &i2c3;
9 i2c2 = &i2c4;
Michael Walle2a20ed12021-10-13 18:14:15 +020010 ethernet2 = &enetc_port2;
11 ethernet3 = &enetc_port3;
Michael Walle36ba7642020-10-15 23:08:57 +020012 };
13
Michael Wallef5253fb2020-11-18 17:46:01 +010014 binman: binman {
Michael Walle927f0c42021-09-29 13:39:10 +020015 multiple-images;
16 };
17};
18
19&binman {
20 u_boot_rom: u-boot-rom {
Michael Walle36ba7642020-10-15 23:08:57 +020021 filename = "u-boot.rom";
22 pad-byte = <0xff>;
23
24 u-boot-spl {
25 };
26
27 fit {
28 offset = <CONFIG_SPL_PAD_TO>;
29 description = "FIT image with multiple configurations";
Michael Wallefb559062022-02-25 18:21:56 +053030 fit,fdt-list = "of-list";
Michael Walle36ba7642020-10-15 23:08:57 +020031
32 images {
33 uboot {
34 description = "U-Boot";
35 type = "firmware";
36 os = "u-boot";
37 arch = "arm";
38 compression = "none";
Simon Glass72cc5382022-10-20 18:22:39 -060039 load = <CONFIG_TEXT_BASE>;
Michael Walle36ba7642020-10-15 23:08:57 +020040
41 u-boot-nodtb {
42 };
43 };
44
Michael Wallefb559062022-02-25 18:21:56 +053045 @fdt-SEQ {
46 description = "NAME";
Michael Walle36ba7642020-10-15 23:08:57 +020047 type = "flat_dt";
Michael Walle36ba7642020-10-15 23:08:57 +020048 compression = "none";
Michael Walle36ba7642020-10-15 23:08:57 +020049 };
50 };
51
52 configurations {
Michael Wallefb559062022-02-25 18:21:56 +053053 default = "@config-DEFAULT-SEQ";
Michael Walle36ba7642020-10-15 23:08:57 +020054
Michael Wallefb559062022-02-25 18:21:56 +053055 @config-SEQ {
56 description = "NAME";
Michael Walle36ba7642020-10-15 23:08:57 +020057 firmware = "uboot";
Michael Wallefb559062022-02-25 18:21:56 +053058 fdt = "fdt-SEQ";
Michael Walleba3aa6b2021-01-08 00:08:58 +010059 };
Michael Walle36ba7642020-10-15 23:08:57 +020060 };
61 };
62 };
63};
64
Michael Walle927f0c42021-09-29 13:39:10 +020065&binman {
66 u-boot-update {
67 filename = "u-boot.update";
68
69 fit {
70 description = "FIT update image";
71
72 images {
73 u-boot-bin {
74 description = "U-Boot";
75 type = "firmware";
76 os = "u-boot";
77 arch = "arm";
78 compression = "none";
79 load = <0>; /* unused */
80
81 blob {
82 filename = "u-boot.rom";
83 };
84 };
85 };
86 };
87 };
88};
89
Michael Walle898a8be2021-03-26 19:40:59 +010090#ifdef CONFIG_SL28_ENABLE_SER0_CONSOLE
91/ {
92 chosen {
93 stdout-path = "serial2:115200n8";
94 };
95};
96#endif
97
Michael Wallef5253fb2020-11-18 17:46:01 +010098#ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31
Michael Walle927f0c42021-09-29 13:39:10 +020099&u_boot_rom {
Michael Wallef5253fb2020-11-18 17:46:01 +0100100 fit {
101 images {
102 bl31 {
103 description = "ARM Trusted Firmware (bl31)";
104 type = "firmware";
105 arch = "arm";
106 os = "arm-trusted-firmware";
107 compression = "none";
108 load = <CONFIG_SL28_BL31_ENTRY_ADDR>;
109 entry = <CONFIG_SL28_BL31_ENTRY_ADDR>;
110
111 blob-ext {
112 filename = "bl31.bin";
113 };
114 };
115 };
116
117 configurations {
Michael Wallefb559062022-02-25 18:21:56 +0530118 @config-SEQ {
Michael Walleba3aa6b2021-01-08 00:08:58 +0100119 firmware = "bl31";
120 loadables = "uboot";
121 };
Michael Wallef5253fb2020-11-18 17:46:01 +0100122 };
123 };
124};
125#endif
126
Michael Walle76427fb2020-11-18 17:46:02 +0100127#ifdef CONFIG_SL28_SPL_LOADS_OPTEE_BL32
Michael Walle927f0c42021-09-29 13:39:10 +0200128&u_boot_rom {
Michael Walle76427fb2020-11-18 17:46:02 +0100129 fit {
130 images {
131 bl32 {
132 description = "OP-TEE Trusted OS (bl32)";
133 type = "firmware";
134 arch = "arm";
135 os = "tee";
136 compression = "none";
137 load = <CONFIG_SL28_BL32_ENTRY_ADDR>;
138 entry = <CONFIG_SL28_BL32_ENTRY_ADDR>;
139
140 blob-ext {
141 filename = "tee.bin";
142 };
143 };
144 };
145
146 configurations {
Michael Wallefb559062022-02-25 18:21:56 +0530147 @config-SEQ {
Michael Walleba3aa6b2021-01-08 00:08:58 +0100148 loadables = "uboot", "bl32";
149 };
Michael Walle76427fb2020-11-18 17:46:02 +0100150 };
151 };
152};
153#endif
154
Michael Walle36ba7642020-10-15 23:08:57 +0200155&fspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700156 bootph-all;
Michael Walle36ba7642020-10-15 23:08:57 +0200157 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700158 bootph-all;
Michael Walle36ba7642020-10-15 23:08:57 +0200159 };
160};
161
162&dspi2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700163 bootph-all;
Michael Walle36ba7642020-10-15 23:08:57 +0200164};
165
Michael Walle2a20ed12021-10-13 18:14:15 +0200166&esdhc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700167 bootph-all;
Michael Walle36ba7642020-10-15 23:08:57 +0200168};
169
170&esdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700171 bootph-all;
Michael Walle36ba7642020-10-15 23:08:57 +0200172};
173
Michael Walle898a8be2021-03-26 19:40:59 +0100174&lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700175 bootph-all;
Michael Walle898a8be2021-03-26 19:40:59 +0100176};
177
Michael Walle2a20ed12021-10-13 18:14:15 +0200178&duart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700179 bootph-all;
Michael Walle36ba7642020-10-15 23:08:57 +0200180};
181
Michael Walle0a908fb2021-10-13 18:14:25 +0200182/*
183 * u-boot will enable the device in the linux device tree in place. Because
184 * we are using the linux device tree, we have to enable the PCI controller
185 * ourselves.
186 */
187&pcie1 {
188 status = "okay";
189};
190
191&pcie2 {
192 status = "okay";
193};
194
Michael Walle773a7f82021-10-13 18:14:27 +0200195&sata {
196 status = "okay";
197};
198
Michael Wallea81b2e82021-10-13 18:14:03 +0200199&soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700200 bootph-all;
Michael Wallea81b2e82021-10-13 18:14:03 +0200201};
202
Michael Walle36ba7642020-10-15 23:08:57 +0200203&sysclk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700204 bootph-all;
Michael Walle36ba7642020-10-15 23:08:57 +0200205};