Fabio Estevam | adac83a | 2011-09-06 09:05:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | */ |
| 19 | |
| 20 | #include <common.h> |
| 21 | #include <asm/io.h> |
Fabio Estevam | 1de48fa | 2012-10-23 06:34:49 +0000 | [diff] [blame] | 22 | #include <asm/gpio.h> |
Fabio Estevam | adac83a | 2011-09-06 09:05:43 +0000 | [diff] [blame] | 23 | #include <asm/arch/imx-regs.h> |
| 24 | #include <asm/arch/imx25-pinmux.h> |
| 25 | #include <asm/arch/sys_proto.h> |
Fabio Estevam | 1de48fa | 2012-10-23 06:34:49 +0000 | [diff] [blame] | 26 | #include <asm/arch/clock.h> |
| 27 | #include <mmc.h> |
| 28 | #include <fsl_esdhc.h> |
Fabio Estevam | 90c3aae | 2012-10-23 06:34:53 +0000 | [diff] [blame] | 29 | #include <i2c.h> |
Fabio Estevam | 592fd4e | 2012-12-11 04:58:02 +0000 | [diff] [blame] | 30 | #include <power/pmic.h> |
Fabio Estevam | 90c3aae | 2012-10-23 06:34:53 +0000 | [diff] [blame] | 31 | #include <fsl_pmic.h> |
| 32 | #include <mc34704.h> |
Fabio Estevam | 1de48fa | 2012-10-23 06:34:49 +0000 | [diff] [blame] | 33 | |
Fabio Estevam | 90c3aae | 2012-10-23 06:34:53 +0000 | [diff] [blame] | 34 | #define FEC_RESET_B IMX_GPIO_NR(2, 3) |
| 35 | #define FEC_ENABLE_B IMX_GPIO_NR(4, 8) |
Fabio Estevam | 1de48fa | 2012-10-23 06:34:49 +0000 | [diff] [blame] | 36 | #define CARD_DETECT IMX_GPIO_NR(2, 1) |
Fabio Estevam | adac83a | 2011-09-06 09:05:43 +0000 | [diff] [blame] | 37 | |
| 38 | DECLARE_GLOBAL_DATA_PTR; |
| 39 | |
Fabio Estevam | 1de48fa | 2012-10-23 06:34:49 +0000 | [diff] [blame] | 40 | #ifdef CONFIG_FSL_ESDHC |
| 41 | struct fsl_esdhc_cfg esdhc_cfg[1] = { |
| 42 | {IMX_MMC_SDHC1_BASE}, |
| 43 | }; |
| 44 | #endif |
| 45 | |
Fabio Estevam | 90c3aae | 2012-10-23 06:34:53 +0000 | [diff] [blame] | 46 | static void mx25pdk_fec_init(void) |
| 47 | { |
| 48 | struct iomuxc_mux_ctl *muxctl; |
| 49 | struct iomuxc_pad_ctl *padctl; |
| 50 | u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); |
| 51 | u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; |
| 52 | |
| 53 | /* FEC pin init is generic */ |
| 54 | mx25_fec_init_pins(); |
| 55 | |
| 56 | muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; |
| 57 | padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; |
| 58 | /* |
| 59 | * Set up FEC_RESET_B and FEC_ENABLE_B |
| 60 | * |
| 61 | * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12 |
| 62 | * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17 |
| 63 | */ |
| 64 | writel(gpio_mux_mode, &muxctl->pad_d12); |
| 65 | writel(gpio_mux_mode, &muxctl->pad_a17); |
| 66 | |
| 67 | writel(0x0, &padctl->pad_d12); |
| 68 | writel(0x0, &padctl->pad_a17); |
| 69 | |
| 70 | /* Assert RESET and ENABLE low */ |
| 71 | gpio_direction_output(FEC_RESET_B, 0); |
| 72 | gpio_direction_output(FEC_ENABLE_B, 0); |
| 73 | |
| 74 | udelay(10); |
| 75 | |
| 76 | /* Deassert RESET and ENABLE */ |
| 77 | gpio_set_value(FEC_RESET_B, 1); |
| 78 | gpio_set_value(FEC_ENABLE_B, 1); |
| 79 | |
| 80 | /* Setup I2C pins so that PMIC can turn on PHY supply */ |
| 81 | writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk); |
| 82 | writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat); |
| 83 | writel(0x1E8, &padctl->pad_i2c1_clk); |
| 84 | writel(0x1E8, &padctl->pad_i2c1_dat); |
| 85 | } |
| 86 | |
Fabio Estevam | adac83a | 2011-09-06 09:05:43 +0000 | [diff] [blame] | 87 | int dram_init(void) |
| 88 | { |
| 89 | /* dram_init must store complete ramsize in gd->ram_size */ |
| 90 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
| 91 | PHYS_SDRAM_1_SIZE); |
| 92 | return 0; |
| 93 | } |
| 94 | |
Fabio Estevam | adac83a | 2011-09-06 09:05:43 +0000 | [diff] [blame] | 95 | int board_early_init_f(void) |
| 96 | { |
| 97 | mx25_uart1_init_pins(); |
| 98 | |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | int board_init(void) |
| 103 | { |
Fabio Estevam | adac83a | 2011-09-06 09:05:43 +0000 | [diff] [blame] | 104 | /* address of boot parameters */ |
| 105 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
| 106 | |
| 107 | return 0; |
| 108 | } |
Fabio Estevam | 1de48fa | 2012-10-23 06:34:49 +0000 | [diff] [blame] | 109 | |
Fabio Estevam | 90c3aae | 2012-10-23 06:34:53 +0000 | [diff] [blame] | 110 | int board_late_init(void) |
| 111 | { |
| 112 | struct pmic *p; |
Fabio Estevam | 592fd4e | 2012-12-11 04:58:02 +0000 | [diff] [blame] | 113 | int ret; |
Fabio Estevam | 90c3aae | 2012-10-23 06:34:53 +0000 | [diff] [blame] | 114 | |
| 115 | mx25pdk_fec_init(); |
| 116 | |
Fabio Estevam | 592fd4e | 2012-12-11 04:58:02 +0000 | [diff] [blame] | 117 | ret = pmic_init(I2C_PMIC); |
| 118 | if (ret) |
| 119 | return ret; |
| 120 | |
| 121 | p = pmic_get("FSL_PMIC"); |
| 122 | if (!p) |
| 123 | return -ENODEV; |
| 124 | |
Fabio Estevam | 90c3aae | 2012-10-23 06:34:53 +0000 | [diff] [blame] | 125 | /* Turn on Ethernet PHY supply */ |
| 126 | pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE); |
| 127 | |
| 128 | return 0; |
| 129 | } |
| 130 | |
Fabio Estevam | 1de48fa | 2012-10-23 06:34:49 +0000 | [diff] [blame] | 131 | #ifdef CONFIG_FSL_ESDHC |
| 132 | int board_mmc_getcd(struct mmc *mmc) |
| 133 | { |
| 134 | struct iomuxc_mux_ctl *muxctl; |
| 135 | struct iomuxc_pad_ctl *padctl; |
| 136 | u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); |
| 137 | |
| 138 | /* |
| 139 | * Set up the Card Detect pin. |
| 140 | * |
| 141 | * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15 |
| 142 | * |
| 143 | */ |
| 144 | muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; |
| 145 | padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; |
| 146 | |
| 147 | writel(gpio_mux_mode, &muxctl->pad_a15); |
| 148 | writel(0x0, &padctl->pad_a15); |
| 149 | |
| 150 | gpio_direction_input(CARD_DETECT); |
| 151 | return !gpio_get_value(CARD_DETECT); |
| 152 | } |
| 153 | |
| 154 | int board_mmc_init(bd_t *bis) |
| 155 | { |
| 156 | struct iomuxc_mux_ctl *muxctl; |
| 157 | u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; |
| 158 | |
| 159 | muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; |
| 160 | writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd); |
| 161 | writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk); |
| 162 | writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0); |
| 163 | writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1); |
| 164 | writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2); |
| 165 | writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3); |
| 166 | |
| 167 | esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); |
| 168 | return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
| 169 | } |
| 170 | #endif |
Fabio Estevam | adac83a | 2011-09-06 09:05:43 +0000 | [diff] [blame] | 171 | |
| 172 | int checkboard(void) |
| 173 | { |
| 174 | puts("Board: MX25PDK\n"); |
| 175 | |
| 176 | return 0; |
| 177 | } |