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Linus Walleij717b0a82012-08-04 05:21:28 +00001/*
2 * (C) Copyright 2012
3 * Linaro
4 * Linus Walleij <linus.walleij@linaro.org>
5 * Common ARM Integrator configuration settings
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Linus Walleij717b0a82012-08-04 05:21:28 +00008 */
9
Linus Walleij717b0a82012-08-04 05:21:28 +000010#define CONFIG_SYS_TEXT_BASE 0x01000000
11#define CONFIG_SYS_MEMTEST_START 0x100000
12#define CONFIG_SYS_MEMTEST_END 0x10000000
Linus Walleij717b0a82012-08-04 05:21:28 +000013#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
14#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
15#define CONFIG_SYS_LONGHELP
16#define CONFIG_SYS_HUSH_PARSER
17#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
18#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
19#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
20#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
21#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
22
Linus Walleij616d9a02015-07-27 11:22:48 +020023/* Serial port PL010/PL011 through the device model */
24#define CONFIG_PL01X_SERIAL
25#define CONFIG_BAUDRATE 38400
26#define CONFIG_CONS_INDEX 0
27
Linus Walleij717b0a82012-08-04 05:21:28 +000028#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
29#define CONFIG_SETUP_MEMORY_TAGS
Linus Walleij44796de2013-04-03 19:19:20 +000030#define CONFIG_OF_LIBFDT /* enable passing a Device Tree */
Linus Walleij717b0a82012-08-04 05:21:28 +000031#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
Linus Walleija20cac32014-06-23 11:15:16 +020032#define CONFIG_SYS_GENERIC_BOARD
Linus Walleij717b0a82012-08-04 05:21:28 +000033
34/*
35 * There are various dependencies on the core module (CM) fitted
36 * Users should refer to their CM user guide
37 */
38#include "armcoremodule.h"
39
40/*
41 * Initialize and remap the core module, use SPD to detect memory size
42 * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
43 * the core module has a CM_INIT register
44 * then the U-Boot initialisation code will
45 * e.g. ARM Boot Monitor or pre-loader is repeated once
46 * (to re-initialise any existing CM_INIT settings to safe values).
47 *
48 * This is usually not the desired behaviour since the platform
49 * will either reboot into the ARM monitor (or pre-loader)
50 * or continuously cycle thru it without U-Boot running,
51 * depending upon the setting of Integrator/CP switch S2-4.
52 *
53 * However it may be needed if Integrator/CP switch S2-1
54 * is set OFF to boot direct into U-Boot.
55 * In that case comment out the line below.
56 */
57#define CONFIG_CM_INIT
58#define CONFIG_CM_REMAP
59#define CONFIG_CM_SPD_DETECT
60
61/*
62 * The ARM boot monitor initializes the board.
63 * However, the default U-Boot code also performs the initialization.
64 * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
65 * - see documentation supplied with board for details of how to choose the
66 * image to run at reset/power up
67 * e.g. whether the ARM Boot Monitor runs before U-Boot
68 */
69/* #define CONFIG_SKIP_LOWLEVEL_INIT */
70
71/*
72 * The ARM boot monitor does not relocate U-Boot.
73 * However, the default U-Boot code performs the relocation check,
74 * and may relocate the code if the memory map is changed.
75 * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
76 */
77/* #define SKIP_CONFIG_RELOCATE_UBOOT */
78
79
80/*
81 * Physical Memory Map
82 */
83#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
84#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
85#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
86#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
87#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
88#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
89 CONFIG_SYS_INIT_RAM_SIZE - \
90 GENERATED_GBL_DATA_SIZE)
91#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
Linus Walleij48fd6152015-04-05 01:48:33 +020092
93/*
94 * FLASH and environment organization
95 * Top varies according to amount fitted
96 * Reserve top 4 blocks of flash
97 * - ARM Boot Monitor
98 * - Unused
99 * - SIB block
100 * - U-Boot environment
101 */
Linus Walleij48fd6152015-04-05 01:48:33 +0200102#define CONFIG_CMD_ARMFLASH
103#define CONFIG_SYS_FLASH_CFI 1
104#define CONFIG_FLASH_CFI_DRIVER 1
105#define CONFIG_SYS_FLASH_BASE 0x24000000
106#define CONFIG_SYS_MAX_FLASH_BANKS 1
107
108/* Timeout values in ticks */
109#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
110#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
111#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
112#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */