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Jean-Christophe PLAGNIOL-VILLARD06a819c2009-06-13 20:50:02 +02001/*
2 * include/asm-arm/macro.h
3 *
4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARD06a819c2009-06-13 20:50:02 +02007 */
8
9#ifndef __ASM_ARM_MACRO_H__
10#define __ASM_ARM_MACRO_H__
11#ifdef __ASSEMBLY__
12
13/*
14 * These macros provide a convenient way to write 8, 16 and 32 bit data
15 * to any address.
16 * Registers r4 and r5 are used, any data in these registers are
17 * overwritten by the macros.
18 * The macros are valid for any ARM architecture, they do not implement
19 * any memory barriers so caution is recommended when using these when the
20 * caches are enabled or on a multi-core system.
21 */
22
23.macro write32, addr, data
24 ldr r4, =\addr
25 ldr r5, =\data
26 str r5, [r4]
27.endm
28
29.macro write16, addr, data
30 ldr r4, =\addr
31 ldrh r5, =\data
32 strh r5, [r4]
33.endm
34
35.macro write8, addr, data
36 ldr r4, =\addr
37 ldrb r5, =\data
38 strb r5, [r4]
39.endm
40
41/*
42 * This macro generates a loop that can be used for delays in the code.
43 * Register r4 is used, any data in this register is overwritten by the
44 * macro.
45 * The macro is valid for any ARM architeture. The actual time spent in the
46 * loop will vary from CPU to CPU though.
47 */
48
49.macro wait_timer, time
50 ldr r4, =\time
511:
52 nop
53 subs r4, r4, #1
54 bcs 1b
55.endm
56
57#endif /* __ASSEMBLY__ */
58#endif /* __ASM_ARM_MACRO_H__ */