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git01.mediatek.com / filogic / uboot / e09528028716fbf019cc08f0de1e5f2cf51c255e / . / include / configs / salvator-x.h
blob: 0ac39003266e25ec02bd07071fb6822e799fe1cf [file] [log] [blame]
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900[diff] [blame]1/*
2 * include/configs/salvator-x.h
3 * This file is Salvator-X board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __SALVATOR_X_H
11#define __SALVATOR_X_H
12
13#undef DEBUG
14
15#define CONFIG_RCAR_BOARD_STRING "Salvator-X"
16
17#include "rcar-gen3-common.h"
18
19/* SCIF */
20#define CONFIG_SCIF_CONSOLE
21#define CONFIG_CONS_SCIF2
22#define CONFIG_CONS_INDEX 2
Marek Vasutff178222017-05-13 15:57:45 +0200[diff] [blame]23#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900[diff] [blame]24
25/* [A] Hyper Flash */
26/* use to RPC(SPI Multi I/O Bus Controller) */
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900[diff] [blame]27
Marek Vasut51e80062017-05-13 15:57:47 +0200[diff] [blame]28/* Ethernet RAVB */
29#define CONFIG_NET_MULTI
30#define CONFIG_PHY_MICREL
31#define CONFIG_BITBANGMII
32#define CONFIG_BITBANGMII_MULTI
33
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900[diff] [blame]34/* Board Clock */
35/* XTAL_CLK : 33.33MHz */
36#define RCAR_XTAL_CLK 33333333u
37#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
38/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
Marek Vasutff178222017-05-13 15:57:45 +0200[diff] [blame]39/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900[diff] [blame]40#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
41#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
42#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
Marek Vasutff178222017-05-13 15:57:45 +0200[diff] [blame]43#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900[diff] [blame]44
45/* Generic Timer Definitions (use in assembler source) */
46#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
47
48/* Generic Interrupt Controller Definitions */
49#define CONFIG_GICV2
50#define GICD_BASE 0xF1010000
51#define GICC_BASE 0xF1020000
52
Marek Vasutc16ed0b2017-05-13 15:57:48 +0200[diff] [blame]53/* i2c */
54#define CONFIG_SYS_I2C
55#define CONFIG_SYS_I2C_SH
56#define CONFIG_SYS_I2C_SLAVE 0x60
57#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
58#define CONFIG_SYS_I2C_SH_SPEED0 400000
59#define CONFIG_SH_I2C_DATA_HIGH 4
60#define CONFIG_SH_I2C_DATA_LOW 5
61#define CONFIG_SH_I2C_CLOCK 10000000
62
63#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
64
Marek Vasut4659a622017-05-13 15:57:49 +0200[diff] [blame]65/* USB */
66#ifdef CONFIG_R8A7795
67#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
68#else
69#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
70#endif
71
Marek Vasut5abb39b2017-05-13 15:57:46 +0200[diff] [blame]72/* SDHI */
73#define CONFIG_SH_SDHI_FREQ 200000000
74
75/* Environment in eMMC, at the end of 2nd "boot sector" */
76#define CONFIG_ENV_IS_IN_MMC
77#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
78#define CONFIG_SYS_MMC_ENV_DEV 1
79#define CONFIG_SYS_MMC_ENV_PART 2
80
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900[diff] [blame]81/* Module stop status bits */
82/* MFIS, SCIF1 */
83#define CONFIG_SMSTP2_ENA 0x00002040
Marek Vasuta21e30e2017-05-13 15:57:51 +0200[diff] [blame]84/* SCIF2 */
85#define CONFIG_SMSTP3_ENA 0x00000400
Nobuhiro Iwamatsufdf7c652016-04-01 03:51:36 +0900[diff] [blame]86/* INTC-AP, IRQC */
87#define CONFIG_SMSTP4_ENA 0x00000180
88
89#endif /* __SALVATOR_X_H */