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Marek Vasutc140e982011-11-08 23:18:08 +00001/*
2 * Freescale i.MX28 I2C Register Definitions
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#ifndef __MX28_REGS_I2C_H__
24#define __MX28_REGS_I2C_H__
25
Stefan Roese136f3f42013-04-09 21:06:07 +000026#include <asm/imx-common/regs-common.h>
Marek Vasutc140e982011-11-08 23:18:08 +000027
28#ifndef __ASSEMBLY__
Otavio Salvador22f4ff92012-08-05 09:05:31 +000029struct mxs_i2c_regs {
Otavio Salvador5309b002012-08-05 09:05:30 +000030 mxs_reg_32(hw_i2c_ctrl0)
31 mxs_reg_32(hw_i2c_timing0)
32 mxs_reg_32(hw_i2c_timing1)
33 mxs_reg_32(hw_i2c_timing2)
34 mxs_reg_32(hw_i2c_ctrl1)
35 mxs_reg_32(hw_i2c_stat)
36 mxs_reg_32(hw_i2c_queuectrl)
37 mxs_reg_32(hw_i2c_queuestat)
38 mxs_reg_32(hw_i2c_queuecmd)
39 mxs_reg_32(hw_i2c_queuedata)
40 mxs_reg_32(hw_i2c_data)
41 mxs_reg_32(hw_i2c_debug0)
42 mxs_reg_32(hw_i2c_debug1)
43 mxs_reg_32(hw_i2c_version)
Marek Vasutc140e982011-11-08 23:18:08 +000044};
45#endif
46
47#define I2C_CTRL_SFTRST (1 << 31)
48#define I2C_CTRL_CLKGATE (1 << 30)
49#define I2C_CTRL_RUN (1 << 29)
50#define I2C_CTRL_PREACK (1 << 27)
51#define I2C_CTRL_ACKNOWLEDGE (1 << 26)
52#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25)
53#define I2C_CTRL_MULTI_MASTER (1 << 23)
54#define I2C_CTRL_CLOCK_HELD (1 << 22)
55#define I2C_CTRL_RETAIN_CLOCK (1 << 21)
56#define I2C_CTRL_POST_SEND_STOP (1 << 20)
57#define I2C_CTRL_PRE_SEND_START (1 << 19)
58#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18)
59#define I2C_CTRL_MASTER_MODE (1 << 17)
60#define I2C_CTRL_DIRECTION (1 << 16)
61#define I2C_CTRL_XFER_COUNT_MASK 0xffff
62#define I2C_CTRL_XFER_COUNT_OFFSET 0
63
64#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16)
65#define I2C_TIMING0_HIGH_COUNT_OFFSET 16
66#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff
67#define I2C_TIMING0_RCV_COUNT_OFFSET 0
68
69#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16)
70#define I2C_TIMING1_LOW_COUNT_OFFSET 16
71#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff
72#define I2C_TIMING1_XMIT_COUNT_OFFSET 0
73
74#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16)
75#define I2C_TIMING2_BUS_FREE_OFFSET 16
76#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff
77#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0
78
79#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30)
80#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29)
81#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28)
82#define I2C_CTRL1_ACK_MODE (1 << 27)
83#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26)
84#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25)
85#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24)
86#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16)
87#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16
88#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15)
89#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14)
90#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13)
91#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12)
92#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11)
93#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10)
94#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9)
95#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8)
96#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7)
97#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6)
98#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5)
99#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4)
100#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3)
101#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2)
102#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1)
103#define I2C_CTRL1_SLAVE_IRQ (1 << 0)
104
105#define I2C_STAT_MASTER_PRESENT (1 << 31)
106#define I2C_STAT_SLAVE_PRESENT (1 << 30)
107#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29)
108#define I2C_STAT_GOT_A_NAK (1 << 28)
109#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16)
110#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16
111#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15)
112#define I2C_STAT_SLAVE_FOUND (1 << 14)
113#define I2C_STAT_SLAVE_SEARCHING (1 << 13)
114#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12)
115#define I2C_STAT_BUS_BUSY (1 << 11)
116#define I2C_STAT_CLK_GEN_BUSY (1 << 10)
117#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9)
118#define I2C_STAT_SLAVE_BUSY (1 << 8)
119#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7)
120#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6)
121#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5)
122#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4)
123#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3)
124#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2)
125#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1)
126#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0)
127
128#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16)
129#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16
130#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8)
131#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8
132#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5)
133#define I2C_QUEUECTRL_RD_CLEAR (1 << 4)
134#define I2C_QUEUECTRL_WR_CLEAR (1 << 3)
135#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2)
136#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1)
137#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0)
138
139#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14)
140#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13)
141#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8)
142#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8
143#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6)
144#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5)
145#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f
146#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0
147
148#define I2C_QUEUECMD_PREACK (1 << 27)
149#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26)
150#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25)
151#define I2C_QUEUECMD_MULTI_MASTER (1 << 23)
152#define I2C_QUEUECMD_CLOCK_HELD (1 << 22)
153#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21)
154#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20)
155#define I2C_QUEUECMD_PRE_SEND_START (1 << 19)
156#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18)
157#define I2C_QUEUECMD_MASTER_MODE (1 << 17)
158#define I2C_QUEUECMD_DIRECTION (1 << 16)
159#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff
160#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0
161
162#define I2C_QUEUEDATA_DATA_MASK 0xffffffff
163#define I2C_QUEUEDATA_DATA_OFFSET 0
164
165#define I2C_DATA_DATA_MASK 0xffffffff
166#define I2C_DATA_DATA_OFFSET 0
167
168#define I2C_DEBUG0_DMAREQ (1 << 31)
169#define I2C_DEBUG0_DMAENDCMD (1 << 30)
170#define I2C_DEBUG0_DMAKICK (1 << 29)
171#define I2C_DEBUG0_DMATERMINATE (1 << 28)
172#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26)
173#define I2C_DEBUG0_STATE_VALUE_OFFSET 26
174#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16)
175#define I2C_DEBUG0_DMA_STATE_OFFSET 16
176#define I2C_DEBUG0_START_TOGGLE (1 << 15)
177#define I2C_DEBUG0_STOP_TOGGLE (1 << 14)
178#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13)
179#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12)
180#define I2C_DEBUG0_STATE_LATCH (1 << 11)
181#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10)
182#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff
183#define I2C_DEBUG0_STATE_STATE_OFFSET 0
184
185#define I2C_DEBUG1_I2C_CLK_IN (1 << 31)
186#define I2C_DEBUG1_I2C_DATA_IN (1 << 30)
187#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24)
188#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24
189#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16)
190#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16
191#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9)
192#define I2C_DEBUG1_LST_MODE_OFFSET 9
193#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8)
194#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4)
195#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3)
196#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2)
197#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1)
198#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0)
199
200#define I2C_VERSION_MAJOR_MASK (0xff << 24)
201#define I2C_VERSION_MAJOR_OFFSET 24
202#define I2C_VERSION_MINOR_MASK (0xff << 16)
203#define I2C_VERSION_MINOR_OFFSET 16
204#define I2C_VERSION_STEP_MASK 0xffff
205#define I2C_VERSION_STEP_OFFSET 0
206
207#endif /* __MX28_REGS_I2C_H__ */