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git01.mediatek.com / filogic / uboot / e0665b12c256c0547fcbe45f1cbbf2628575f039 / . / include / configs / lager.h
blob: e830c6df0acdf64c1a3f45961ee9436b74a75505 [file] [log] [blame]
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]1/*
2 * include/configs/lager.h
3 * This file is lager board configuration.
4 *
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +0900[diff] [blame]5 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __LAGER_H
11#define __LAGER_H
12
13#undef DEBUG
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]14#define CONFIG_R8A7790
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]15#define CONFIG_RMOBILE_BOARD_STRING "Lager"
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]16
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +0900[diff] [blame]17#include "rcar-gen2-common.h"
Nobuhiro Iwamatsue59703e2014-03-31 15:22:31 +0900[diff] [blame]18
Nobuhiro Iwamatsu2af4b002014-10-31 16:16:26 +0900[diff] [blame]19#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
20#define CONFIG_SYS_TEXT_BASE 0xB0000000
21#else
Nobuhiro Iwamatsu00e4c8a2014-01-08 10:32:22 +0900[diff] [blame]22#define CONFIG_SYS_TEXT_BASE 0xE8080000
Nobuhiro Iwamatsu2af4b002014-10-31 16:16:26 +0900[diff] [blame]23#endif
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]24
25/* STACK */
Nobuhiro Iwamatsu2af4b002014-10-31 16:16:26 +0900[diff] [blame]26#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
27#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
28#else
29#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
30#endif
31#define STACK_AREA_SIZE 0xC000
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]32#define LOW_LEVEL_MERAM_STACK \
33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34
35/* MEMORY */
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +0900[diff] [blame]36#define RCAR_GEN2_SDRAM_BASE 0x40000000
37#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
38#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]39
40/* SCIF */
41#define CONFIG_SCIF_CONSOLE
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]42
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +0900[diff] [blame]43/* SPI */
Nobuhiro Iwamatsu00e4c8a2014-01-08 10:32:22 +0900[diff] [blame]44#define CONFIG_SPI
45#define CONFIG_SPI_FLASH_BAR
46#define CONFIG_SH_QSPI
47#define CONFIG_SPI_FLASH
48#define CONFIG_SPI_FLASH_SPANSION
49#define CONFIG_SYS_NO_FLASH
50
Nobuhiro Iwamatsu0929b742013-10-20 20:28:24 +0900[diff] [blame]51/* SH Ether */
52#define CONFIG_NET_MULTI
53#define CONFIG_SH_ETHER
54#define CONFIG_SH_ETHER_USE_PORT 0
55#define CONFIG_SH_ETHER_PHY_ADDR 0x1
56#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
57#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
58#define CONFIG_SH_ETHER_CACHE_WRITEBACK
59#define CONFIG_SH_ETHER_CACHE_INVALIDATE
60#define CONFIG_PHYLIB
61#define CONFIG_PHY_MICREL
62#define CONFIG_BITBANGMII
63#define CONFIG_BITBANGMII_MULTI
64
Nobuhiro Iwamatsue2652e52013-09-30 10:08:40 +0900[diff] [blame]65/* I2C */
66#define CONFIG_SYS_I2C
67#define CONFIG_SYS_I2C_RCAR
Nobuhiro Iwamatsue2652e52013-09-30 10:08:40 +0900[diff] [blame]68#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
Nobuhiro Iwamatsue2652e52013-09-30 10:08:40 +0900[diff] [blame]69#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
Nobuhiro Iwamatsue2652e52013-09-30 10:08:40 +0900[diff] [blame]70#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
Nobuhiro Iwamatsue2652e52013-09-30 10:08:40 +0900[diff] [blame]71#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
72#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
73
Nobuhiro Iwamatsua99b6b52013-10-10 09:13:41 +0900[diff] [blame]74#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
75
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]76/* Board Clock */
Nobuhiro Iwamatsu18d337a2014-03-31 14:03:07 +0900[diff] [blame]77#define RMOBILE_XTAL_CLK 20000000u
78#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
79#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
80#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]81#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
82#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
Nobuhiro Iwamatsue2652e52013-09-30 10:08:40 +0900[diff] [blame]83#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]84
85#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]86
Nobuhiro Iwamatsu12b4fb02014-03-27 14:14:58 +0900[diff] [blame]87/* USB */
88#define CONFIG_USB_EHCI
89#define CONFIG_USB_EHCI_RMOBILE
Nobuhiro Iwamatsua9c085f2014-07-28 15:29:31 +0900[diff] [blame]90#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Nobuhiro Iwamatsu12b4fb02014-03-27 14:14:58 +0900[diff] [blame]91#define CONFIG_USB_STORAGE
92
Nobuhiro Iwamatsubaf336a2014-12-03 15:30:30 +0900[diff] [blame]93/* MMC */
94#define CONFIG_MMC
95#define CONFIG_CMD_MMC
96#define CONFIG_GENERIC_MMC
97
98#define CONFIG_SH_MMCIF
99#define CONFIG_SH_MMCIF_ADDR 0xEE220000
100#define CONFIG_SH_MMCIF_CLK 97500000
101
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +0900[diff] [blame]102/* Module stop status bits */
103/* INTC-RT */
104#define CONFIG_SMSTP0_ENA 0x00400000
105/* MSIF */
106#define CONFIG_SMSTP2_ENA 0x00002000
107/* INTC-SYS, IRQC */
108#define CONFIG_SMSTP4_ENA 0x00000180
109/* SCIF0 */
110#define CONFIG_SMSTP7_ENA 0x00200000
111
Nobuhiro Iwamatsu4ca383a2014-11-21 10:19:32 +0900[diff] [blame]112/* SDHI */
113#define CONFIG_SH_SDHI_FREQ 97500000
114
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +0900[diff] [blame]115#endif /* __LAGER_H */