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git01.mediatek.com / filogic / uboot / e065fb1a08c9deb85633ff823468f1e65ca05dc5 / . / configs / T1024RDB_SPIFLASH_defconfig
blob: 1c25d219dc8154eafa67dad3db76b8a7f7d210f7 [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_PPC=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0x30001000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]3CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]4CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini56fd1e12020-11-30 12:50:32 -0500[diff] [blame]5CONFIG_SYS_MEMTEST_START=0x00200000
6CONFIG_SYS_MEMTEST_END=0x00400000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]7CONFIG_ENV_SIZE=0x2000
8CONFIG_ENV_OFFSET=0x100000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]9CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinie065fb12021-08-28 21:34:49 -0400[diff] [blame^]10CONFIG_SYS_MALLOC_LEN=0xa00000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]11CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]12CONFIG_SPL_TEXT_BASE=0xFFFD8000
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]13CONFIG_SPL_SERIAL_SUPPORT=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]14CONFIG_SPL_DRIVERS_MISC=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]15CONFIG_SPL=y
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]16CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassb24fdca2016-09-12 23:18:58 -0600[diff] [blame]17CONFIG_SPL_SPI_SUPPORT=y
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]18CONFIG_MPC85xx=y
York Suna5ca1422016-11-18 12:45:44 -0800[diff] [blame]19CONFIG_TARGET_T1024RDB=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]20CONFIG_FIT=y
21CONFIG_FIT_VERBOSE=y
22CONFIG_OF_BOARD_SETUP=y
23CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rini9ff815a2021-08-24 23:11:49 -0400[diff] [blame]24CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
25CONFIG_RAMBOOT_PBL=y
26CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
27CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_spi_rcw.cfg"
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]28CONFIG_BOOTDELAY=10
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]29CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]30CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]31CONFIG_BOARD_EARLY_INIT_F=y
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]32CONFIG_BOARD_EARLY_INIT_R=y
Tom Rini4abdf142021-08-17 17:59:41 -0400[diff] [blame]33CONFIG_ID_EEPROM=y
Tom Rini623d67e2018-02-06 12:15:38 -0500[diff] [blame]34# CONFIG_SPL_FRAMEWORK is not set
Tom Rinie5678e42019-06-01 14:20:25 -0400[diff] [blame]35CONFIG_SPL_SPI_BOOT=y
36CONFIG_SPL_FSL_PBL=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]37CONFIG_SPL_ENV_SUPPORT=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]38CONFIG_SPL_I2C=y
Simon Glass7db65a82016-09-12 23:18:45 -0600[diff] [blame]39CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]40CONFIG_HUSH_PARSER=y
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]41CONFIG_CMD_IMLS=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]42CONFIG_CMD_GREPENV=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]43CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
44CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
45CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]46CONFIG_CMD_MEMTEST=y
Mario Six00518992018-03-28 14:38:14 +0200[diff] [blame]47CONFIG_SYS_ALT_MEMTEST=y
Tom Rini52f34042020-06-23 08:20:07 -0400[diff] [blame]48CONFIG_CMD_DM=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]49CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]50CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]51CONFIG_CMD_USB=y
52CONFIG_CMD_DHCP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]53CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]54CONFIG_CMD_PING=y
Siva Durga Prasad Paladugu8e45f1a2018-06-19 12:24:23 +0200[diff] [blame]55CONFIG_MP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]56CONFIG_CMD_EXT2=y
57CONFIG_CMD_FAT=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]58CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
59CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
Hou Zhiqiangfe812802019-08-20 09:35:26 +0000[diff] [blame]60CONFIG_OF_CONTROL=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]61CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]62CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]63CONFIG_DM=y
Tom Rinia5c4d402017-03-01 16:51:58 -0500[diff] [blame]64CONFIG_FSL_CAAM=y
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]65CONFIG_SYS_FSL_DDR3=y
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]66CONFIG_DDR_ECC=y
67CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]68CONFIG_DM_I2C=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]69CONFIG_SPL_SYS_I2C_LEGACY=y
Tom Rinib1b13072021-08-18 23:12:37 -0400[diff] [blame]70CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
Tom Rinibe94c762021-08-18 23:12:35 -0400[diff] [blame]71CONFIG_SYS_I2C_FSL=y
72CONFIG_SYS_FSL_I2C_OFFSET=0x118000
73CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
74CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]75CONFIG_SYS_I2C_EEPROM_ADDR=0x50
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]76CONFIG_FSL_ESDHC=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]77CONFIG_MTD=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]78CONFIG_MTD_NOR_FLASH=y
79CONFIG_FLASH_CFI_DRIVER=y
80CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
81CONFIG_FLASH_CFI_MTD=y
82CONFIG_SYS_FLASH_CFI=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]83CONFIG_DM_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]84CONFIG_SF_DEFAULT_MODE=0
85CONFIG_SF_DEFAULT_SPEED=10000000
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]86CONFIG_SPI_FLASH_STMICRO=y
Alexandru Gagniucd83e98c2017-08-01 17:19:59 -0700[diff] [blame]87CONFIG_PHYLIB=y
Jeremy Gebbenabe3edf2018-09-18 15:49:35 -0600[diff] [blame]88CONFIG_PHY_AQUANTIA=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]89CONFIG_PHY_REALTEK=y
Madalin Bucur273abc32020-04-30 16:00:15 +0300[diff] [blame]90CONFIG_DM_ETH=y
91CONFIG_DM_MDIO=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]92CONFIG_E1000=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]93CONFIG_FMAN_ENET=y
94CONFIG_MII=y
Hou Zhiqiang088d2fd2019-08-27 11:03:37 +0000[diff] [blame]95CONFIG_PCIE_FSL=y
Tom Rinifa911f82019-05-12 07:59:12 -0400[diff] [blame]96CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]97CONFIG_DM_RTC=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]98CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]99CONFIG_SPI=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]100CONFIG_DM_SPI=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]101CONFIG_FSL_ESPI=y
Tom Rini6e9cb112016-09-08 16:31:26 -0400[diff] [blame]102CONFIG_USB=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]103CONFIG_USB_STORAGE=y
Marek Szyprowski795dc7d2020-06-03 14:43:40 +0200[diff] [blame]104CONFIG_ADDR_MAP=y
105CONFIG_SYS_NUM_ADDR_MAP=64