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wdenkef5fe752003-03-12 10:41:04 +00001/*
2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc824x.h>
26#include <asm/processor.h>
27
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020028#if defined(CONFIG_ENV_IS_IN_FLASH)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020029# ifndef CONFIG_ENV_ADDR
30# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
wdenkef5fe752003-03-12 10:41:04 +000031# endif
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020032# ifndef CONFIG_ENV_SIZE
33# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
wdenkef5fe752003-03-12 10:41:04 +000034# endif
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020035# ifndef CONFIG_ENV_SECT_SIZE
36# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
wdenkef5fe752003-03-12 10:41:04 +000037# endif
38#endif
39
40#define FLASH_BANK_SIZE 0x800000
41#define MAIN_SECT_SIZE 0x40000
42#define PARAM_SECT_SIZE 0x8000
43
wdenk9e930b62004-06-19 21:19:10 +000044flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
wdenkef5fe752003-03-12 10:41:04 +000045
wdenk9e930b62004-06-19 21:19:10 +000046static int write_data (flash_info_t * info, ulong dest, ulong * data);
47static void write_via_fpu (vu_long * addr, ulong * data);
48static __inline__ unsigned long get_msr (void);
49static __inline__ void set_msr (unsigned long msr);
wdenkef5fe752003-03-12 10:41:04 +000050
51/*---------------------------------------------------------------------*/
52#undef DEBUG_FLASH
53
54/*---------------------------------------------------------------------*/
55#ifdef DEBUG_FLASH
56#define DEBUGF(fmt,args...) printf(fmt ,##args)
57#else
58#define DEBUGF(fmt,args...)
59#endif
60/*---------------------------------------------------------------------*/
61
62/*-----------------------------------------------------------------------
63 */
64
wdenk9e930b62004-06-19 21:19:10 +000065unsigned long flash_init (void)
wdenkef5fe752003-03-12 10:41:04 +000066{
wdenk9e930b62004-06-19 21:19:10 +000067 int i, j;
68 ulong size = 0;
69 uchar tempChar;
70 vu_long *tmpaddr;
wdenkef5fe752003-03-12 10:41:04 +000071
wdenk9e930b62004-06-19 21:19:10 +000072 /* Enable flash writes on CPC45 */
wdenkef5fe752003-03-12 10:41:04 +000073
wdenk9e930b62004-06-19 21:19:10 +000074 tempChar = BOARD_CTRL;
wdenkef5fe752003-03-12 10:41:04 +000075
wdenk9e930b62004-06-19 21:19:10 +000076 tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
wdenkef5fe752003-03-12 10:41:04 +000077
wdenk9e930b62004-06-19 21:19:10 +000078 tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
wdenkef5fe752003-03-12 10:41:04 +000079
wdenk9e930b62004-06-19 21:19:10 +000080 BOARD_CTRL = tempChar;
wdenkef5fe752003-03-12 10:41:04 +000081
wdenk9e930b62004-06-19 21:19:10 +000082 __asm__ volatile ("sync\n eieio");
wdenkef5fe752003-03-12 10:41:04 +000083
wdenk9e930b62004-06-19 21:19:10 +000084 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
85 vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
wdenkef5fe752003-03-12 10:41:04 +000086
wdenk9e930b62004-06-19 21:19:10 +000087 addr[0] = 0x00900090;
wdenkef5fe752003-03-12 10:41:04 +000088
wdenk9e930b62004-06-19 21:19:10 +000089 __asm__ volatile ("sync\n eieio");
wdenkef5fe752003-03-12 10:41:04 +000090
wdenk9e930b62004-06-19 21:19:10 +000091 udelay (100);
wdenkef5fe752003-03-12 10:41:04 +000092
wdenk9e930b62004-06-19 21:19:10 +000093 DEBUGF ("Flash bank # %d:\n"
94 "\tManuf. ID @ 0x%08lX: 0x%08lX\n"
95 "\tDevice ID @ 0x%08lX: 0x%08lX\n",
96 i,
97 (ulong) (&addr[0]), addr[0],
98 (ulong) (&addr[2]), addr[2]);
wdenkef5fe752003-03-12 10:41:04 +000099
wdenkef5fe752003-03-12 10:41:04 +0000100
wdenk9e930b62004-06-19 21:19:10 +0000101 if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
102 (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
wdenkef5fe752003-03-12 10:41:04 +0000103
wdenk9e930b62004-06-19 21:19:10 +0000104 flash_info[i].flash_id =
105 (FLASH_MAN_INTEL & FLASH_VENDMASK) |
106 (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
wdenkef5fe752003-03-12 10:41:04 +0000107
wdenk9e930b62004-06-19 21:19:10 +0000108 } else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
109 && (addr[2] == addr[3])
110 && (addr[2] == INTEL_ID_28F160C3T)) {
wdenkef5fe752003-03-12 10:41:04 +0000111
wdenk9e930b62004-06-19 21:19:10 +0000112 flash_info[i].flash_id =
113 (FLASH_MAN_INTEL & FLASH_VENDMASK) |
114 (INTEL_ID_28F160C3T & FLASH_TYPEMASK);
115
wdenkef5fe752003-03-12 10:41:04 +0000116 } else {
wdenk9e930b62004-06-19 21:19:10 +0000117 flash_info[i].flash_id = FLASH_UNKNOWN;
118 addr[0] = 0xFFFFFFFF;
119 goto Done;
120 }
121
122 DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
123
124 addr[0] = 0xFFFFFFFF;
125
126 flash_info[i].size = FLASH_BANK_SIZE;
127 flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
128 memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
129 for (j = 0; j < flash_info[i].sector_count; j++) {
130 if (j > 30) {
131 flash_info[i].start[j] = CFG_FLASH_BASE +
132 i * FLASH_BANK_SIZE +
133 (MAIN_SECT_SIZE * 31) + (j -
134 31) *
135 PARAM_SECT_SIZE;
136 } else {
137 flash_info[i].start[j] = CFG_FLASH_BASE +
138 i * FLASH_BANK_SIZE +
139 j * MAIN_SECT_SIZE;
140 }
wdenkef5fe752003-03-12 10:41:04 +0000141 }
wdenk9e930b62004-06-19 21:19:10 +0000142
143 /* unlock sectors, if 160C3T */
144
145 for (j = 0; j < flash_info[i].sector_count; j++) {
146 tmpaddr = (vu_long *) flash_info[i].start[j];
147
148 if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
149 (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
150 tmpaddr[0] = 0x00600060;
151 tmpaddr[0] = 0x00D000D0;
152 tmpaddr[1] = 0x00600060;
153 tmpaddr[1] = 0x00D000D0;
154 }
155 }
156
157 size += flash_info[i].size;
158
159 addr[0] = 0x00FF00FF;
160 addr[1] = 0x00FF00FF;
wdenkef5fe752003-03-12 10:41:04 +0000161 }
wdenkef5fe752003-03-12 10:41:04 +0000162
wdenk9e930b62004-06-19 21:19:10 +0000163 /* Protect monitor and environment sectors
164 */
wdenkef5fe752003-03-12 10:41:04 +0000165#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
wdenk9e930b62004-06-19 21:19:10 +0000166 flash_protect (FLAG_PROTECT_SET,
167 CFG_MONITOR_BASE,
168 CFG_MONITOR_BASE + monitor_flash_len - 1,
169 &flash_info[1]);
wdenkef5fe752003-03-12 10:41:04 +0000170#else
wdenk9e930b62004-06-19 21:19:10 +0000171 flash_protect (FLAG_PROTECT_SET,
172 CFG_MONITOR_BASE,
173 CFG_MONITOR_BASE + monitor_flash_len - 1,
174 &flash_info[0]);
wdenkef5fe752003-03-12 10:41:04 +0000175#endif
176
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200177#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
178#if CONFIG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
wdenk9e930b62004-06-19 21:19:10 +0000179 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200180 CONFIG_ENV_ADDR,
181 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
wdenkef5fe752003-03-12 10:41:04 +0000182#else
wdenk9e930b62004-06-19 21:19:10 +0000183 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200184 CONFIG_ENV_ADDR,
185 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
wdenkef5fe752003-03-12 10:41:04 +0000186#endif
187#endif
188
189Done:
wdenk9e930b62004-06-19 21:19:10 +0000190 return size;
wdenkef5fe752003-03-12 10:41:04 +0000191}
192
193/*-----------------------------------------------------------------------
194 */
195void flash_print_info (flash_info_t * info)
196{
197 int i;
198
199 switch ((i = info->flash_id & FLASH_VENDMASK)) {
200 case (FLASH_MAN_INTEL & FLASH_VENDMASK):
201 printf ("Intel: ");
202 break;
203 default:
204 printf ("Unknown Vendor 0x%04x ", i);
205 break;
206 }
207
208 switch ((i = info->flash_id & FLASH_TYPEMASK)) {
209 case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
210 printf ("28F160F3T (16Mbit)\n");
211 break;
wdenk9e930b62004-06-19 21:19:10 +0000212
213 case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
214 printf ("28F160C3T (16Mbit)\n");
215 break;
216
wdenkef5fe752003-03-12 10:41:04 +0000217 default:
218 printf ("Unknown Chip Type 0x%04x\n", i);
219 goto Done;
220 break;
221 }
222
223 printf (" Size: %ld MB in %d Sectors\n",
wdenk9e930b62004-06-19 21:19:10 +0000224 info->size >> 20, info->sector_count);
wdenkef5fe752003-03-12 10:41:04 +0000225
226 printf (" Sector Start Addresses:");
227 for (i = 0; i < info->sector_count; i++) {
228 if ((i % 5) == 0) {
229 printf ("\n ");
230 }
231 printf (" %08lX%s", info->start[i],
wdenk9e930b62004-06-19 21:19:10 +0000232 info->protect[i] ? " (RO)" : " ");
wdenkef5fe752003-03-12 10:41:04 +0000233 }
234 printf ("\n");
235
236Done:
237 return;
238}
239
240/*-----------------------------------------------------------------------
241 */
242
wdenk9e930b62004-06-19 21:19:10 +0000243int flash_erase (flash_info_t * info, int s_first, int s_last)
wdenkef5fe752003-03-12 10:41:04 +0000244{
245 int flag, prot, sect;
246 ulong start, now, last;
247
248 DEBUGF ("Erase flash bank %d sect %d ... %d\n",
249 info - &flash_info[0], s_first, s_last);
250
251 if ((s_first < 0) || (s_first > s_last)) {
252 if (info->flash_id == FLASH_UNKNOWN) {
253 printf ("- missing\n");
254 } else {
255 printf ("- no sectors to erase\n");
256 }
257 return 1;
258 }
259
260 if ((info->flash_id & FLASH_VENDMASK) !=
261 (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
262 printf ("Can erase only Intel flash types - aborted\n");
263 return 1;
264 }
265
266 prot = 0;
wdenk9e930b62004-06-19 21:19:10 +0000267 for (sect = s_first; sect <= s_last; ++sect) {
wdenkef5fe752003-03-12 10:41:04 +0000268 if (info->protect[sect]) {
269 prot++;
270 }
271 }
272
273 if (prot) {
wdenk9e930b62004-06-19 21:19:10 +0000274 printf ("- Warning: %d protected sectors will not be erased!\n", prot);
wdenkef5fe752003-03-12 10:41:04 +0000275 } else {
276 printf ("\n");
277 }
278
279 start = get_timer (0);
wdenk9e930b62004-06-19 21:19:10 +0000280 last = start;
wdenkef5fe752003-03-12 10:41:04 +0000281 /* Start erase on unprotected sectors */
wdenk9e930b62004-06-19 21:19:10 +0000282 for (sect = s_first; sect <= s_last; sect++) {
wdenkef5fe752003-03-12 10:41:04 +0000283 if (info->protect[sect] == 0) { /* not protected */
wdenk9e930b62004-06-19 21:19:10 +0000284 vu_long *addr = (vu_long *) (info->start[sect]);
wdenkef5fe752003-03-12 10:41:04 +0000285
286 DEBUGF ("Erase sect %d @ 0x%08lX\n",
wdenk9e930b62004-06-19 21:19:10 +0000287 sect, (ulong) addr);
wdenkef5fe752003-03-12 10:41:04 +0000288
289 /* Disable interrupts which might cause a timeout
290 * here.
291 */
wdenk9e930b62004-06-19 21:19:10 +0000292 flag = disable_interrupts ();
wdenkef5fe752003-03-12 10:41:04 +0000293
294 addr[0] = 0x00500050; /* clear status register */
295 addr[0] = 0x00200020; /* erase setup */
296 addr[0] = 0x00D000D0; /* erase confirm */
297
298 addr[1] = 0x00500050; /* clear status register */
299 addr[1] = 0x00200020; /* erase setup */
300 addr[1] = 0x00D000D0; /* erase confirm */
301
302 /* re-enable interrupts if necessary */
303 if (flag)
wdenk9e930b62004-06-19 21:19:10 +0000304 enable_interrupts ();
wdenkef5fe752003-03-12 10:41:04 +0000305
306 /* wait at least 80us - let's wait 1 ms */
307 udelay (1000);
308
309 while (((addr[0] & 0x00800080) != 0x00800080) ||
wdenk9e930b62004-06-19 21:19:10 +0000310 ((addr[1] & 0x00800080) != 0x00800080)) {
311 if ((now = get_timer (start)) >
312 CFG_FLASH_ERASE_TOUT) {
wdenkef5fe752003-03-12 10:41:04 +0000313 printf ("Timeout\n");
wdenk9e930b62004-06-19 21:19:10 +0000314 addr[0] = 0x00B000B0; /* suspend erase */
315 addr[0] = 0x00FF00FF; /* to read mode */
wdenkef5fe752003-03-12 10:41:04 +0000316 return 1;
317 }
318
319 /* show that we're waiting */
wdenk9e930b62004-06-19 21:19:10 +0000320 if ((now - last) > 1000) { /* every second */
wdenkef5fe752003-03-12 10:41:04 +0000321 putc ('.');
322 last = now;
323 }
324 }
325
326 addr[0] = 0x00FF00FF;
327 }
328 }
329 printf (" done\n");
330 return 0;
331}
332
333/*-----------------------------------------------------------------------
334 * Copy memory to flash, returns:
335 * 0 - OK
336 * 1 - write timeout
337 * 2 - Flash not erased
338 * 4 - Flash not identified
339 */
340
341#define FLASH_WIDTH 8 /* flash bus width in bytes */
342
wdenk9e930b62004-06-19 21:19:10 +0000343int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
wdenkef5fe752003-03-12 10:41:04 +0000344{
345 ulong wp, cp, msr;
346 int l, rc, i;
347 ulong data[2];
348 ulong *datah = &data[0];
349 ulong *datal = &data[1];
350
351 DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
wdenk9e930b62004-06-19 21:19:10 +0000352 addr, (ulong) src, cnt);
wdenkef5fe752003-03-12 10:41:04 +0000353
354 if (info->flash_id == FLASH_UNKNOWN) {
355 return 4;
356 }
357
wdenk9e930b62004-06-19 21:19:10 +0000358 msr = get_msr ();
359 set_msr (msr | MSR_FP);
wdenkef5fe752003-03-12 10:41:04 +0000360
wdenk9e930b62004-06-19 21:19:10 +0000361 wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */
wdenkef5fe752003-03-12 10:41:04 +0000362
363 /*
364 * handle unaligned start bytes
365 */
366 if ((l = addr - wp) != 0) {
367 *datah = *datal = 0;
368
369 for (i = 0, cp = wp; i < l; i++, cp++) {
370 if (i >= 4) {
371 *datah = (*datah << 8) |
wdenk9e930b62004-06-19 21:19:10 +0000372 ((*datal & 0xFF000000) >> 24);
wdenkef5fe752003-03-12 10:41:04 +0000373 }
374
wdenk9e930b62004-06-19 21:19:10 +0000375 *datal = (*datal << 8) | (*(uchar *) cp);
wdenkef5fe752003-03-12 10:41:04 +0000376 }
377 for (; i < FLASH_WIDTH && cnt > 0; ++i) {
wdenk9e930b62004-06-19 21:19:10 +0000378 char tmp = *src++;
wdenkef5fe752003-03-12 10:41:04 +0000379
380 if (i >= 4) {
381 *datah = (*datah << 8) |
wdenk9e930b62004-06-19 21:19:10 +0000382 ((*datal & 0xFF000000) >> 24);
wdenkef5fe752003-03-12 10:41:04 +0000383 }
384
385 *datal = (*datal << 8) | tmp;
wdenk9e930b62004-06-19 21:19:10 +0000386 --cnt;
387 ++cp;
wdenkef5fe752003-03-12 10:41:04 +0000388 }
389
390 for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
391 if (i >= 4) {
392 *datah = (*datah << 8) |
wdenk9e930b62004-06-19 21:19:10 +0000393 ((*datal & 0xFF000000) >> 24);
wdenkef5fe752003-03-12 10:41:04 +0000394 }
395
wdenk9e930b62004-06-19 21:19:10 +0000396 *datal = (*datah << 8) | (*(uchar *) cp);
wdenkef5fe752003-03-12 10:41:04 +0000397 }
398
wdenk9e930b62004-06-19 21:19:10 +0000399 if ((rc = write_data (info, wp, data)) != 0) {
400 set_msr (msr);
wdenkef5fe752003-03-12 10:41:04 +0000401 return (rc);
402 }
403
404 wp += FLASH_WIDTH;
405 }
406
407 /*
408 * handle FLASH_WIDTH aligned part
409 */
410 while (cnt >= FLASH_WIDTH) {
wdenk9e930b62004-06-19 21:19:10 +0000411 *datah = *(ulong *) src;
412 *datal = *(ulong *) (src + 4);
413 if ((rc = write_data (info, wp, data)) != 0) {
414 set_msr (msr);
wdenkef5fe752003-03-12 10:41:04 +0000415 return (rc);
416 }
wdenk9e930b62004-06-19 21:19:10 +0000417 wp += FLASH_WIDTH;
wdenkef5fe752003-03-12 10:41:04 +0000418 cnt -= FLASH_WIDTH;
419 src += FLASH_WIDTH;
420 }
421
422 if (cnt == 0) {
wdenk9e930b62004-06-19 21:19:10 +0000423 set_msr (msr);
wdenkef5fe752003-03-12 10:41:04 +0000424 return (0);
425 }
426
427 /*
428 * handle unaligned tail bytes
429 */
430 *datah = *datal = 0;
431 for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
wdenk9e930b62004-06-19 21:19:10 +0000432 char tmp = *src++;
wdenkef5fe752003-03-12 10:41:04 +0000433
434 if (i >= 4) {
wdenk9e930b62004-06-19 21:19:10 +0000435 *datah = (*datah << 8) | ((*datal & 0xFF000000) >>
436 24);
wdenkef5fe752003-03-12 10:41:04 +0000437 }
438
439 *datal = (*datal << 8) | tmp;
wdenkef5fe752003-03-12 10:41:04 +0000440 --cnt;
441 }
442
443 for (; i < FLASH_WIDTH; ++i, ++cp) {
444 if (i >= 4) {
wdenk9e930b62004-06-19 21:19:10 +0000445 *datah = (*datah << 8) | ((*datal & 0xFF000000) >>
446 24);
wdenkef5fe752003-03-12 10:41:04 +0000447 }
448
wdenk9e930b62004-06-19 21:19:10 +0000449 *datal = (*datal << 8) | (*(uchar *) cp);
wdenkef5fe752003-03-12 10:41:04 +0000450 }
451
wdenk9e930b62004-06-19 21:19:10 +0000452 rc = write_data (info, wp, data);
453 set_msr (msr);
wdenkef5fe752003-03-12 10:41:04 +0000454
455 return (rc);
456}
457
458/*-----------------------------------------------------------------------
459 * Write a word to Flash, returns:
460 * 0 - OK
461 * 1 - write timeout
462 * 2 - Flash not erased
463 */
wdenk9e930b62004-06-19 21:19:10 +0000464static int write_data (flash_info_t * info, ulong dest, ulong * data)
wdenkef5fe752003-03-12 10:41:04 +0000465{
wdenk9e930b62004-06-19 21:19:10 +0000466 vu_long *addr = (vu_long *) dest;
wdenkef5fe752003-03-12 10:41:04 +0000467 ulong start;
468 int flag;
469
470 /* Check if Flash is (sufficiently) erased */
471 if (((addr[0] & data[0]) != data[0]) ||
wdenk9e930b62004-06-19 21:19:10 +0000472 ((addr[1] & data[1]) != data[1])) {
wdenkef5fe752003-03-12 10:41:04 +0000473 return (2);
474 }
475 /* Disable interrupts which might cause a timeout here */
wdenk9e930b62004-06-19 21:19:10 +0000476 flag = disable_interrupts ();
wdenkef5fe752003-03-12 10:41:04 +0000477
wdenk9e930b62004-06-19 21:19:10 +0000478 addr[0] = 0x00400040; /* write setup */
479 write_via_fpu (addr, data);
wdenkef5fe752003-03-12 10:41:04 +0000480
481 /* re-enable interrupts if necessary */
482 if (flag)
wdenk9e930b62004-06-19 21:19:10 +0000483 enable_interrupts ();
wdenkef5fe752003-03-12 10:41:04 +0000484
485 start = get_timer (0);
486
487 while (((addr[0] & 0x00800080) != 0x00800080) ||
wdenk9e930b62004-06-19 21:19:10 +0000488 ((addr[1] & 0x00800080) != 0x00800080)) {
489 if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
wdenkef5fe752003-03-12 10:41:04 +0000490 addr[0] = 0x00FF00FF; /* restore read mode */
491 return (1);
492 }
493 }
494
495 addr[0] = 0x00FF00FF; /* restore read mode */
496
497 return (0);
498}
499
500/*-----------------------------------------------------------------------
501 */
wdenk9e930b62004-06-19 21:19:10 +0000502static void write_via_fpu (vu_long * addr, ulong * data)
wdenkef5fe752003-03-12 10:41:04 +0000503{
wdenk9e930b62004-06-19 21:19:10 +0000504 __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
505 __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
wdenkef5fe752003-03-12 10:41:04 +0000506}
wdenk9e930b62004-06-19 21:19:10 +0000507
wdenkef5fe752003-03-12 10:41:04 +0000508/*-----------------------------------------------------------------------
509 */
wdenk9e930b62004-06-19 21:19:10 +0000510static __inline__ unsigned long get_msr (void)
wdenkef5fe752003-03-12 10:41:04 +0000511{
wdenk9e930b62004-06-19 21:19:10 +0000512 unsigned long msr;
wdenkef5fe752003-03-12 10:41:04 +0000513
wdenk9e930b62004-06-19 21:19:10 +0000514 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
515
516 return msr;
wdenkef5fe752003-03-12 10:41:04 +0000517}
518
wdenk9e930b62004-06-19 21:19:10 +0000519static __inline__ void set_msr (unsigned long msr)
wdenkef5fe752003-03-12 10:41:04 +0000520{
wdenk9e930b62004-06-19 21:19:10 +0000521 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
wdenkef5fe752003-03-12 10:41:04 +0000522}