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Kevin Scholz521a4ef2019-10-07 19:26:36 +05301/* SPDX-License-Identifier: BSD-3-Clause */
Dave Gerlachd712b362021-05-11 10:22:11 -05002/*
3 * Cadence DDR Driver
4 *
Bryan Brattlof85b5cc82022-10-24 16:53:28 -05005 * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
Kevin Scholz521a4ef2019-10-07 19:26:36 +05307 */
Dave Gerlachd712b362021-05-11 10:22:11 -05008
Kevin Scholz521a4ef2019-10-07 19:26:36 +05309#ifndef LPDDR4_STRUCTS_IF_H
10#define LPDDR4_STRUCTS_IF_H
11
12#include <linux/types.h>
13#include "lpddr4_if.h"
14
Dave Gerlachd712b362021-05-11 10:22:11 -050015struct lpddr4_config_s {
16 struct lpddr4_ctlregs_s *ctlbase;
Kevin Scholz521a4ef2019-10-07 19:26:36 +053017 lpddr4_infocallback infohandler;
Kevin Scholz521a4ef2019-10-07 19:26:36 +053018 lpddr4_ctlcallback ctlinterrupthandler;
Kevin Scholz521a4ef2019-10-07 19:26:36 +053019 lpddr4_phyindepcallback phyindepinterrupthandler;
20};
21
Dave Gerlachd712b362021-05-11 10:22:11 -050022struct lpddr4_privatedata_s {
23 struct lpddr4_ctlregs_s *ctlbase;
Kevin Scholz521a4ef2019-10-07 19:26:36 +053024 lpddr4_infocallback infohandler;
Kevin Scholz521a4ef2019-10-07 19:26:36 +053025 lpddr4_ctlcallback ctlinterrupthandler;
Kevin Scholz521a4ef2019-10-07 19:26:36 +053026 lpddr4_phyindepcallback phyindepinterrupthandler;
Aswath Govindraju7bd88442022-01-25 20:56:28 +053027 void *ddr_instance;
Kevin Scholz521a4ef2019-10-07 19:26:36 +053028};
29
Dave Gerlachd712b362021-05-11 10:22:11 -050030struct lpddr4_debuginfo_s {
31 u8 pllerror;
32 u8 iocaliberror;
33 u8 rxoffseterror;
34 u8 catraingerror;
35 u8 wrlvlerror;
36 u8 gatelvlerror;
37 u8 readlvlerror;
38 u8 dqtrainingerror;
Kevin Scholz521a4ef2019-10-07 19:26:36 +053039};
40
Dave Gerlachd712b362021-05-11 10:22:11 -050041struct lpddr4_fspmoderegs_s {
42 u8 mr1data_fn[LPDDR4_INTR_MAX_CS];
43 u8 mr2data_fn[LPDDR4_INTR_MAX_CS];
44 u8 mr3data_fn[LPDDR4_INTR_MAX_CS];
45 u8 mr11data_fn[LPDDR4_INTR_MAX_CS];
46 u8 mr12data_fn[LPDDR4_INTR_MAX_CS];
47 u8 mr13data_fn[LPDDR4_INTR_MAX_CS];
48 u8 mr14data_fn[LPDDR4_INTR_MAX_CS];
49 u8 mr22data_fn[LPDDR4_INTR_MAX_CS];
Kevin Scholz521a4ef2019-10-07 19:26:36 +053050};
51
52#endif /* LPDDR4_STRUCTS_IF_H */