| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 2 | /* |
| Albert ARIBAUD | 340983d | 2011-04-22 19:41:02 +0200 | [diff] [blame] | 3 | * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> |
| Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 4 | * |
| 5 | * Based on original Kirkwood 88F6182 support which is |
| 6 | * (C) Copyright 2009 |
| 7 | * Marvell Semiconductor <www.marvell.com> |
| 8 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
| 9 | * |
| 10 | * Header file for Feroceon CPU core 88F5182 SOC. |
| Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #ifndef _CONFIG_88F5182_H |
| 14 | #define _CONFIG_88F5182_H |
| 15 | |
| 16 | /* SOC specific definitions */ |
| 17 | #define F88F5182_REGS_PHYS_BASE 0xf1000000 |
| 18 | #define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE |
| 19 | |
| 20 | /* TCLK Core Clock defination */ |
| 21 | #define CONFIG_SYS_TCLK 166000000 /* 166MHz */ |
| 22 | |
| 23 | #endif /* _CONFIG_88F5182_H */ |