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git01.mediatek.com / filogic / uboot / e014275ce560cf5d4cc812aa8c94b94627ef19a1 / . / board / bticino / mamoj / spl.c
blob: 4274cc8712346ba0bd5af9a2d813a4dcf809a7e8 [file] [log] [blame]
Jagan Tekie0142752018-05-07 11:21:34 +0530[diff] [blame^]1/*
2 * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
3 * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
4 * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <spl.h>
11
12#include <asm/io.h>
13#include <linux/sizes.h>
14
15#include <asm/arch/clock.h>
16#include <asm/arch/crm_regs.h>
17#include <asm/arch/iomux.h>
18#include <asm/arch/mx6-ddr.h>
19#include <asm/arch/mx6-pins.h>
20#include <asm/arch/sys_proto.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
24#define IMX6SDL_DRIVE_STRENGTH 0x28
25#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
26 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
27
28static iomux_v3_cfg_t const uart3_pads[] = {
29 IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
30 IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
31};
32
33struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
34 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
35 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
36 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
37 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
38 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
39 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
40 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
41 .dram_sdba2 = 0x00000000,
42 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
43 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
44 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
45 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
46 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
47 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
48 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
49 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
50 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
51 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
52 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
53 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
54 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
55 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
56 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
57 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
58 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
59 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
60};
61
62struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
63 .grp_ddr_type = 0x000c0000,
64 .grp_ddrmode_ctl = 0x00020000,
65 .grp_ddrpke = 0x00000000,
66 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
67 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
68 .grp_ddrmode = 0x00020000,
69 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
70 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
71 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
72 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
73 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
74 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
75 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
76 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
77};
78
79static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
80 .mem_speed = 1600,
81 .density = 4,
82 .width = 32,
83 .banks = 8,
84 .rowaddr = 14,
85 .coladdr = 10,
86 .pagesz = 2,
87 .trcd = 1375,
88 .trcmin = 4875,
89 .trasmin = 3500,
90 .SRT = 0,
91};
92
93static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
94 .p0_mpwldectrl0 = 0x0042004b,
95 .p0_mpwldectrl1 = 0x0038003c,
96 .p0_mpdgctrl0 = 0x42340230,
97 .p0_mpdgctrl1 = 0x0228022c,
98 .p0_mprddlctl = 0x42444646,
99 .p0_mpwrdlctl = 0x38382e2e,
100};
101
102static struct mx6_ddr_sysinfo mem_dl = {
103 .dsize = 1,
104 .cs1_mirror = 0,
105 /* config for full 4GB range so that get_mem_size() works */
106 .cs_density = 32,
107 .ncs = 1,
108 .bi_on = 1,
109 .rtt_nom = 1,
110 .rtt_wr = 1,
111 .ralat = 5,
112 .walat = 0,
113 .mif3_mode = 3,
114 .rst_to_cke = 0x23,
115 .sde_to_rst = 0x10,
116 .refsel = 1,
117 .refr = 7,
118};
119
120static void spl_dram_init(void)
121{
122 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
123 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
124
125 udelay(100);
126}
127
128static void ccgr_init(void)
129{
130 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
131
132 writel(0x00003f3f, &ccm->CCGR0);
133 writel(0x0030fc00, &ccm->CCGR1);
134 writel(0x000fc000, &ccm->CCGR2);
135 writel(0x3f300000, &ccm->CCGR3);
136 writel(0xff00f300, &ccm->CCGR4);
137 writel(0x0f0000c3, &ccm->CCGR5);
138 writel(0x000003cc, &ccm->CCGR6);
139}
140
141void board_init_f(ulong dummy)
142{
143 ccgr_init();
144
145 /* setup AIPS and disable watchdog */
146 arch_cpu_init();
147
148 gpr_init();
149
150 /* iomux */
151 SETUP_IOMUX_PADS(uart3_pads);
152
153 /* setup GP timer */
154 timer_init();
155
156 /* UART clocks enabled and gd valid - init serial console */
157 preloader_console_init();
158
159 /* DDR initialization */
160 spl_dram_init();
161}