Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Renesas Technology R0P7785LC0011RL board |
| 4 | * |
| 5 | * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __SH7785LCR_H |
| 9 | #define __SH7785LCR_H |
| 10 | |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 11 | #define CONFIG_CPU_SH7785 1 |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 12 | |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 13 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 14 | "bootdevice=0:1\0" \ |
| 15 | "usbload=usb reset;usbboot;usb stop;bootm\0" |
| 16 | |
Vladimir Zapolskiy | 5e72b84 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 17 | #define CONFIG_DISPLAY_BOARDINFO |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 18 | #undef CONFIG_SHOW_BOOT_PROGRESS |
| 19 | |
| 20 | /* MEMORY */ |
Yoshihiro Shimoda | 22dc9ec | 2009-03-03 15:11:17 +0900 | [diff] [blame] | 21 | #if defined(CONFIG_SH_32BIT) |
Nobuhiro Iwamatsu | f0eb815 | 2010-10-05 16:58:05 +0900 | [diff] [blame] | 22 | /* 0x40000000 - 0x47FFFFFF does not use */ |
| 23 | #define CONFIG_SH_SDRAM_OFFSET (0x8000000) |
| 24 | #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) |
| 25 | #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) |
Yoshihiro Shimoda | 22dc9ec | 2009-03-03 15:11:17 +0900 | [diff] [blame] | 26 | #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) |
| 27 | #define SH7785LCR_FLASH_BASE_1 (0xa0000000) |
| 28 | #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) |
| 29 | #define SH7785LCR_USB_BASE (0xa6000000) |
| 30 | #else |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 31 | #define SH7785LCR_SDRAM_BASE (0x08000000) |
| 32 | #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) |
| 33 | #define SH7785LCR_FLASH_BASE_1 (0xa0000000) |
| 34 | #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) |
| 35 | #define SH7785LCR_USB_BASE (0xb4000000) |
Yoshihiro Shimoda | 22dc9ec | 2009-03-03 15:11:17 +0900 | [diff] [blame] | 36 | #endif |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 37 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 38 | #define CONFIG_SYS_PBSIZE 256 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 40 | |
| 41 | /* SCIF */ |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 42 | #define CONFIG_CONS_SCIF1 1 |
| 43 | #define CONFIG_SCIF_EXT_CLOCK 1 |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 44 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 45 | #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) |
| 46 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 47 | (SH7785LCR_SDRAM_SIZE) - \ |
| 48 | 4 * 1024 * 1024) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
| 50 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 51 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) |
| 53 | #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) |
| 54 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 55 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) |
| 57 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| 58 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 59 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 60 | |
| 61 | /* FLASH */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 62 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
| 63 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 64 | #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) |
| 65 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 66 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 68 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 69 | (0 * SH7785LCR_FLASH_BANK_SIZE) } |
| 70 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
| 72 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
| 73 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
| 74 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 75 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 77 | |
| 78 | /* R8A66597 */ |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 79 | #define CONFIG_USB_R8A66597_HCD |
| 80 | #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE |
| 81 | #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ |
| 82 | #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ |
| 83 | #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ |
| 84 | |
| 85 | /* PCI Controller */ |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 86 | #define CONFIG_SH4_PCI |
| 87 | #define CONFIG_SH7780_PCI |
Yoshihiro Shimoda | 22dc9ec | 2009-03-03 15:11:17 +0900 | [diff] [blame] | 88 | #if defined(CONFIG_SH_32BIT) |
| 89 | #define CONFIG_SH7780_PCI_LSR 0x1ff00001 |
| 90 | #define CONFIG_SH7780_PCI_LAR 0x5f000000 |
| 91 | #define CONFIG_SH7780_PCI_BAR 0x5f000000 |
| 92 | #else |
Yoshihiro Shimoda | 30e055b | 2009-02-25 14:26:42 +0900 | [diff] [blame] | 93 | #define CONFIG_SH7780_PCI_LSR 0x07f00001 |
| 94 | #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE |
| 95 | #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE |
Yoshihiro Shimoda | 22dc9ec | 2009-03-03 15:11:17 +0900 | [diff] [blame] | 96 | #endif |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 97 | #define CONFIG_PCI_SCAN_SHOW 1 |
| 98 | |
| 99 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ |
| 100 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
| 101 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ |
| 102 | |
| 103 | #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ |
| 104 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
| 105 | #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ |
| 106 | |
Yoshihiro Shimoda | 22dc9ec | 2009-03-03 15:11:17 +0900 | [diff] [blame] | 107 | #if defined(CONFIG_SH_32BIT) |
| 108 | #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE |
| 109 | #else |
Yoshihiro Shimoda | f9fc440 | 2009-02-25 14:26:55 +0900 | [diff] [blame] | 110 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE |
Yoshihiro Shimoda | 22dc9ec | 2009-03-03 15:11:17 +0900 | [diff] [blame] | 111 | #endif |
| 112 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE |
Yoshihiro Shimoda | f9fc440 | 2009-02-25 14:26:55 +0900 | [diff] [blame] | 113 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE |
| 114 | |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 115 | /* ENV setting */ |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 116 | #define CONFIG_ENV_OVERWRITE 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 117 | #define CONFIG_ENV_SECT_SIZE (256 * 1024) |
| 118 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
| 120 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 121 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 122 | |
| 123 | /* Board Clock */ |
| 124 | /* The SCIF used external clock. system clock only used timer. */ |
| 125 | #define CONFIG_SYS_CLK_FREQ 50000000 |
Nobuhiro Iwamatsu | e698449 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 126 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Nobuhiro Iwamatsu | 52f73c0 | 2008-08-31 22:45:08 +0900 | [diff] [blame] | 127 | |
| 128 | #endif /* __SH7785LCR_H */ |