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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk9c53f402003-10-15 23:53:47 +00002/*
Kumar Galaa9db4ec2011-01-11 00:52:35 -06003 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk9c53f402003-10-15 23:53:47 +00004 * (C) Copyright 2002,2003 Motorola,Inc.
5 * Xianghua Xiao <X.Xiao@motorola.com>
wdenk9c53f402003-10-15 23:53:47 +00006 */
7
wdenk13eb2212004-07-09 23:27:13 +00008/*
9 * mpc8560ads board configuration file
10 *
11 * Please refer to doc/README.mpc85xx for more info.
12 *
13 * Make sure you change the MAC address and other network params first,
Joe Hershberger76f353e2015-05-04 14:55:14 -050014 * search for CONFIG_SERVERIP, etc. in this file.
wdenk9c53f402003-10-15 23:53:47 +000015 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20/* High Level Configuration Options */
Jon Loeligerf5ad3782005-07-23 10:37:35 -050021#define CONFIG_CPM2 1 /* has CPM2 */
wdenk9c53f402003-10-15 23:53:47 +000022
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020023/*
24 * default CCARBAR is at 0xff700000
25 * assume U-Boot is less than 0.5MB
26 */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020027
Gabor Juhosb4458732013-05-30 07:06:12 +000028#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala7738d5c2008-10-21 11:33:58 -050029#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Andy Fleming8ed11962007-05-08 17:27:43 -050030#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk9c53f402003-10-15 23:53:47 +000031#define CONFIG_ENV_OVERWRITE
Peter Tyserd3d9a502009-09-16 22:03:08 -050032#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk9c53f402003-10-15 23:53:47 +000033
wdenk13eb2212004-07-09 23:27:13 +000034/*
35 * sysclk for MPC85xx
36 *
37 * Two valid values are:
38 * 33000000
39 * 66000000
40 *
41 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk492b9e72004-08-01 23:02:45 +000042 * is likely the desired value here, so that is now the default.
43 * The board, however, can run at 66MHz. In any event, this value
44 * must match the settings of some switches. Details can be found
45 * in the README.mpc85xxads.
wdenk13eb2212004-07-09 23:27:13 +000046 */
47
wdenk492b9e72004-08-01 23:02:45 +000048#ifndef CONFIG_SYS_CLK_FREQ
49#define CONFIG_SYS_CLK_FREQ 33000000
wdenk9c53f402003-10-15 23:53:47 +000050#endif
51
wdenk13eb2212004-07-09 23:27:13 +000052/*
53 * These can be toggled for performance analysis, otherwise use default.
54 */
55#define CONFIG_L2_CACHE /* toggle L2 cache */
56#define CONFIG_BTB /* toggle branch predition */
wdenk13eb2212004-07-09 23:27:13 +000057
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk9c53f402003-10-15 23:53:47 +000059
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
61#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk9c53f402003-10-15 23:53:47 +000062
Timur Tabid8f341c2011-08-04 18:03:41 -050063#define CONFIG_SYS_CCSRBAR 0xe0000000
64#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk9c53f402003-10-15 23:53:47 +000065
Jon Loeliger99d50712008-03-18 11:12:44 -050066/* DDR Setup */
Jon Loeliger99d50712008-03-18 11:12:44 -050067#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
68#define CONFIG_DDR_SPD
69#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk492b9e72004-08-01 23:02:45 +000070
Jon Loeliger99d50712008-03-18 11:12:44 -050071#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
74#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk492b9e72004-08-01 23:02:45 +000075
Jon Loeliger99d50712008-03-18 11:12:44 -050076#define CONFIG_DIMM_SLOTS_PER_CTLR 1
77#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk492b9e72004-08-01 23:02:45 +000078
Jon Loeliger99d50712008-03-18 11:12:44 -050079/* I2C addresses of SPD EEPROMs */
80#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk492b9e72004-08-01 23:02:45 +000081
Jon Loeliger99d50712008-03-18 11:12:44 -050082/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
84#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
85#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
86#define CONFIG_SYS_DDR_TIMING_1 0x37344321
87#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
88#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
89#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
90#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk9c53f402003-10-15 23:53:47 +000091
wdenk13eb2212004-07-09 23:27:13 +000092/*
93 * SDRAM on the Local Bus
94 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020095#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
96#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk9c53f402003-10-15 23:53:47 +000097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
99#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk9c53f402003-10-15 23:53:47 +0000100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
102#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
103#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
104#undef CONFIG_SYS_FLASH_CHECKSUM
105#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
106#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk9c53f402003-10-15 23:53:47 +0000107
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200108#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk13eb2212004-07-09 23:27:13 +0000109
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
111#define CONFIG_SYS_RAMBOOT
wdenk9c53f402003-10-15 23:53:47 +0000112#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#undef CONFIG_SYS_RAMBOOT
wdenk9c53f402003-10-15 23:53:47 +0000114#endif
115
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk13eb2212004-07-09 23:27:13 +0000117
118#undef CONFIG_CLOCKS_IN_MHZ
wdenk9c53f402003-10-15 23:53:47 +0000119
wdenk13eb2212004-07-09 23:27:13 +0000120/*
121 * Local Bus Definitions
122 */
123
124/*
125 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk13eb2212004-07-09 23:27:13 +0000127 *
128 * For BR2, need:
129 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
130 * port-size = 32-bits = BR2[19:20] = 11
131 * no parity checking = BR2[21:22] = 00
132 * SDRAM for MSEL = BR2[24:26] = 011
133 * Valid = BR[31] = 1
134 *
135 * 0 4 8 12 16 20 24 28
136 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
137 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk13eb2212004-07-09 23:27:13 +0000139 * FIXME: the top 17 bits of BR2.
140 */
wdenk9c53f402003-10-15 23:53:47 +0000141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk13eb2212004-07-09 23:27:13 +0000143
144/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk13eb2212004-07-09 23:27:13 +0000146 *
147 * For OR2, need:
148 * 64MB mask for AM, OR2[0:7] = 1111 1100
149 * XAM, OR2[17:18] = 11
150 * 9 columns OR2[19-21] = 010
151 * 13 rows OR2[23-25] = 100
152 * EAD set for extra time OR[31] = 1
153 *
154 * 0 4 8 12 16 20 24 28
155 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
156 */
157
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk13eb2212004-07-09 23:27:13 +0000159
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
161#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
162#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
163#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk13eb2212004-07-09 23:27:13 +0000164
Kumar Gala727c6a62009-03-26 01:34:38 -0500165#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
166 | LSDMR_RFCR5 \
167 | LSDMR_PRETOACT3 \
168 | LSDMR_ACTTORW3 \
169 | LSDMR_BL8 \
170 | LSDMR_WRC2 \
171 | LSDMR_CL3 \
172 | LSDMR_RFEN \
wdenk13eb2212004-07-09 23:27:13 +0000173 )
174
175/*
176 * SDRAM Controller configuration sequence.
177 */
Kumar Gala727c6a62009-03-26 01:34:38 -0500178#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
179#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
180#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
181#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
182#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk13eb2212004-07-09 23:27:13 +0000183
wdenk492b9e72004-08-01 23:02:45 +0000184/*
185 * 32KB, 8-bit wide for ADS config reg
186 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_BR4_PRELIM 0xf8000801
188#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
189#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk9c53f402003-10-15 23:53:47 +0000190
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_INIT_RAM_LOCK 1
192#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200193#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk9c53f402003-10-15 23:53:47 +0000194
Wolfgang Denk0191e472010-10-26 14:34:52 +0200195#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk9c53f402003-10-15 23:53:47 +0000197
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
199#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk9c53f402003-10-15 23:53:47 +0000200
201/* Serial Port */
wdenk13eb2212004-07-09 23:27:13 +0000202#define CONFIG_CONS_ON_SCC /* define if console on SCC */
203#undef CONFIG_CONS_NONE /* define if console on something else */
wdenk9c53f402003-10-15 23:53:47 +0000204
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk9c53f402003-10-15 23:53:47 +0000206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
207
Jon Loeliger43d818f2006-10-20 15:50:15 -0500208/*
209 * I2C
210 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200211#define CONFIG_SYS_I2C
212#define CONFIG_SYS_I2C_FSL
213#define CONFIG_SYS_FSL_I2C_SPEED 400000
214#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
215#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
216#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk9c53f402003-10-15 23:53:47 +0000217
wdenk13eb2212004-07-09 23:27:13 +0000218/* RapidIO MMU */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600219#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala3fe80872008-12-02 16:08:36 -0600220#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600221#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk9c53f402003-10-15 23:53:47 +0000223
wdenk13eb2212004-07-09 23:27:13 +0000224/*
225 * General PCI
Sergei Shtylyov6ffad932006-12-27 22:07:15 +0300226 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk13eb2212004-07-09 23:27:13 +0000227 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600228#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600229#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600230#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600232#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600233#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200234#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
235#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk13eb2212004-07-09 23:27:13 +0000236
237#if defined(CONFIG_PCI)
wdenk13eb2212004-07-09 23:27:13 +0000238#undef CONFIG_EEPRO100
wdenk9c53f402003-10-15 23:53:47 +0000239#undef CONFIG_TULIP
wdenk13eb2212004-07-09 23:27:13 +0000240
241#if !defined(CONFIG_PCI_PNP)
242 #define PCI_ENET0_IOADDR 0xe0000000
243 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denka1be4762008-05-20 16:00:29 +0200244 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk9c53f402003-10-15 23:53:47 +0000245#endif
wdenk13eb2212004-07-09 23:27:13 +0000246
247#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk13eb2212004-07-09 23:27:13 +0000249
250#endif /* CONFIG_PCI */
251
Andy Fleming8ed11962007-05-08 17:27:43 -0500252#ifdef CONFIG_TSEC_ENET
wdenk13eb2212004-07-09 23:27:13 +0000253
Kim Phillips177e58f2007-05-16 16:52:19 -0500254#define CONFIG_TSEC1 1
255#define CONFIG_TSEC1_NAME "TSEC0"
256#define CONFIG_TSEC2 1
257#define CONFIG_TSEC2_NAME "TSEC1"
wdenk13eb2212004-07-09 23:27:13 +0000258#define TSEC1_PHY_ADDR 0
259#define TSEC2_PHY_ADDR 1
260#define TSEC1_PHYIDX 0
261#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500262#define TSEC1_FLAGS TSEC_GIGABIT
263#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500264
265/* Options are: TSEC[0-1] */
266#define CONFIG_ETHPRIME "TSEC0"
wdenk13eb2212004-07-09 23:27:13 +0000267
Andy Fleming8ed11962007-05-08 17:27:43 -0500268#endif /* CONFIG_TSEC_ENET */
269
Wolfgang Denka1be4762008-05-20 16:00:29 +0200270#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
wdenk13eb2212004-07-09 23:27:13 +0000271
Wolfgang Denka1be4762008-05-20 16:00:29 +0200272#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk13eb2212004-07-09 23:27:13 +0000273#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
274
275#if (CONFIG_ETHER_INDEX == 2)
wdenk9c53f402003-10-15 23:53:47 +0000276 /*
277 * - Rx-CLK is CLK13
278 * - Tx-CLK is CLK14
279 * - Select bus for bd/buffers
280 * - Full duplex
281 */
Mike Frysinger109de972011-10-17 05:38:58 +0000282 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
283 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200284 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
285 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk9c53f402003-10-15 23:53:47 +0000286 #define FETH2_RST 0x01
wdenk13eb2212004-07-09 23:27:13 +0000287#elif (CONFIG_ETHER_INDEX == 3)
wdenk9c53f402003-10-15 23:53:47 +0000288 /* need more definitions here for FE3 */
289 #define FETH3_RST 0x80
Wolfgang Denka1be4762008-05-20 16:00:29 +0200290#endif /* CONFIG_ETHER_INDEX */
wdenk13eb2212004-07-09 23:27:13 +0000291
wdenk13eb2212004-07-09 23:27:13 +0000292#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
293
wdenk9c53f402003-10-15 23:53:47 +0000294/*
295 * GPIO pins used for bit-banged MII communications
296 */
297#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellini25e30722009-10-10 12:42:22 +0200298#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
299 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
300#define MDC_DECLARE MDIO_DECLARE
301
wdenk9c53f402003-10-15 23:53:47 +0000302#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
303#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
304#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
305
306#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
307 else iop->pdat &= ~0x00400000
308
309#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
310 else iop->pdat &= ~0x00200000
311
312#define MIIDELAY udelay(1)
wdenk13eb2212004-07-09 23:27:13 +0000313
wdenk9c53f402003-10-15 23:53:47 +0000314#endif
315
wdenk13eb2212004-07-09 23:27:13 +0000316/*
317 * Environment
318 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200319#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200320 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200321 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
322 #define CONFIG_ENV_SIZE 0x2000
wdenk9c53f402003-10-15 23:53:47 +0000323#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200324 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200325 #define CONFIG_ENV_SIZE 0x2000
wdenk9c53f402003-10-15 23:53:47 +0000326#endif
327
wdenk13eb2212004-07-09 23:27:13 +0000328#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200329#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk9c53f402003-10-15 23:53:47 +0000330
Jon Loeligere63319f2007-06-13 13:22:08 -0500331/*
Jon Loeligered26c742007-07-10 09:10:49 -0500332 * BOOTP options
333 */
334#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeligered26c742007-07-10 09:10:49 -0500335
wdenk13eb2212004-07-09 23:27:13 +0000336#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk9c53f402003-10-15 23:53:47 +0000337
338/*
339 * Miscellaneous configurable options
340 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200341#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenk13eb2212004-07-09 23:27:13 +0000342
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk9c53f402003-10-15 23:53:47 +0000344
345/*
346 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500347 * have to be in the first 64 MB of memory, since this is
wdenk9c53f402003-10-15 23:53:47 +0000348 * the maximum mapped by the Linux kernel during initialization.
349 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500350#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
351#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk9c53f402003-10-15 23:53:47 +0000352
Jon Loeligere63319f2007-06-13 13:22:08 -0500353#if defined(CONFIG_CMD_KGDB)
wdenk9c53f402003-10-15 23:53:47 +0000354#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk9c53f402003-10-15 23:53:47 +0000355#endif
356
wdenk492b9e72004-08-01 23:02:45 +0000357/*
358 * Environment Configuration
359 */
wdenk9c53f402003-10-15 23:53:47 +0000360#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming458c3892007-08-16 16:35:02 -0500361#define CONFIG_HAS_ETH0
wdenk54070ab2004-12-31 09:32:47 +0000362#define CONFIG_HAS_ETH1
wdenk54070ab2004-12-31 09:32:47 +0000363#define CONFIG_HAS_ETH2
Kumar Galaf2982fa2007-11-28 22:40:31 -0600364#define CONFIG_HAS_ETH3
wdenk9c53f402003-10-15 23:53:47 +0000365#endif
366
wdenk13eb2212004-07-09 23:27:13 +0000367#define CONFIG_IPADDR 192.168.1.253
368
Mario Six790d8442018-03-28 14:38:20 +0200369#define CONFIG_HOSTNAME "unknown"
Joe Hershberger257ff782011-10-13 13:03:47 +0000370#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000371#define CONFIG_BOOTFILE "your.uImage"
wdenk13eb2212004-07-09 23:27:13 +0000372
373#define CONFIG_SERVERIP 192.168.1.1
374#define CONFIG_GATEWAYIP 192.168.1.1
375#define CONFIG_NETMASK 255.255.255.0
376
377#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
378
wdenk492b9e72004-08-01 23:02:45 +0000379#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming29e484e2008-07-14 20:04:40 -0500380 "netdev=eth0\0" \
381 "consoledev=ttyCPM\0" \
382 "ramdiskaddr=1000000\0" \
383 "ramdiskfile=your.ramdisk.u-boot\0" \
384 "fdtaddr=400000\0" \
385 "fdtfile=mpc8560ads.dtb\0"
wdenk13eb2212004-07-09 23:27:13 +0000386
wdenk492b9e72004-08-01 23:02:45 +0000387#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming29e484e2008-07-14 20:04:40 -0500388 "setenv bootargs root=/dev/nfs rw " \
389 "nfsroot=$serverip:$rootpath " \
390 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
391 "console=$consoledev,$baudrate $othbootargs;" \
392 "tftp $loadaddr $bootfile;" \
393 "tftp $fdtaddr $fdtfile;" \
394 "bootm $loadaddr - $fdtaddr"
wdenk13eb2212004-07-09 23:27:13 +0000395
396#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming29e484e2008-07-14 20:04:40 -0500397 "setenv bootargs root=/dev/ram rw " \
398 "console=$consoledev,$baudrate $othbootargs;" \
399 "tftp $ramdiskaddr $ramdiskfile;" \
400 "tftp $loadaddr $bootfile;" \
401 "tftp $fdtaddr $fdtfile;" \
402 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk13eb2212004-07-09 23:27:13 +0000403
404#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk9c53f402003-10-15 23:53:47 +0000405
406#endif /* __CONFIG_H */