Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2017 NXP |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Ashish Kumar | bc6ceca | 2018-04-13 12:28:45 +0530 | [diff] [blame] | 7 | #include <command.h> |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 8 | #include <netdev.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/fsl_serdes.h> |
| 11 | #include <hwconfig.h> |
| 12 | #include <fsl_mdio.h> |
| 13 | #include <malloc.h> |
Ashish Kumar | bc6ceca | 2018-04-13 12:28:45 +0530 | [diff] [blame] | 14 | #include <phy.h> |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 15 | #include <fm_eth.h> |
| 16 | #include <i2c.h> |
| 17 | #include <miiphy.h> |
Bogdan Purcareata | 33ba939 | 2017-10-05 06:56:53 +0000 | [diff] [blame] | 18 | #include <fsl-mc/fsl_mc.h> |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 19 | #include <fsl-mc/ldpaa_wriop.h> |
| 20 | |
| 21 | #include "../common/qixis.h" |
| 22 | |
| 23 | #include "ls1088a_qixis.h" |
| 24 | |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 25 | #ifdef CONFIG_FSL_MC_ENET |
| 26 | |
| 27 | #define SFP_TX 0 |
| 28 | |
| 29 | /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks. |
| 30 | * Bank 1 -> Lanes A, B, C, D, |
| 31 | * Bank 2 -> Lanes A,B, C, D, |
| 32 | */ |
| 33 | |
| 34 | /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here |
| 35 | * means that the mapping must be determined dynamically, or that the lane |
| 36 | * maps to something other than a board slot. |
| 37 | */ |
| 38 | |
| 39 | static u8 lane_to_slot_fsm1[] = { |
| 40 | 0, 0, 0, 0, 0, 0, 0, 0 |
| 41 | }; |
| 42 | |
| 43 | /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs |
| 44 | * housed. |
| 45 | */ |
| 46 | |
| 47 | static int xqsgii_riser_phy_addr[] = { |
| 48 | XQSGMII_CARD_PHY1_PORT0_ADDR, |
| 49 | XQSGMII_CARD_PHY2_PORT0_ADDR, |
| 50 | XQSGMII_CARD_PHY3_PORT0_ADDR, |
| 51 | XQSGMII_CARD_PHY4_PORT0_ADDR, |
| 52 | XQSGMII_CARD_PHY3_PORT2_ADDR, |
| 53 | XQSGMII_CARD_PHY1_PORT2_ADDR, |
| 54 | XQSGMII_CARD_PHY4_PORT2_ADDR, |
| 55 | XQSGMII_CARD_PHY2_PORT2_ADDR, |
| 56 | }; |
| 57 | |
| 58 | static int sgmii_riser_phy_addr[] = { |
| 59 | SGMII_CARD_PORT1_PHY_ADDR, |
| 60 | SGMII_CARD_PORT2_PHY_ADDR, |
| 61 | SGMII_CARD_PORT3_PHY_ADDR, |
| 62 | SGMII_CARD_PORT4_PHY_ADDR, |
| 63 | }; |
| 64 | |
| 65 | /* Slot2 does not have EMI connections */ |
| 66 | #define EMI_NONE 0xFF |
| 67 | #define EMI1_RGMII1 0 |
| 68 | #define EMI1_RGMII2 1 |
| 69 | #define EMI1_SLOT1 2 |
| 70 | |
| 71 | static const char * const mdio_names[] = { |
| 72 | "LS1088A_QDS_MDIO0", |
| 73 | "LS1088A_QDS_MDIO1", |
| 74 | "LS1088A_QDS_MDIO2", |
| 75 | DEFAULT_WRIOP_MDIO2_NAME, |
| 76 | }; |
| 77 | |
| 78 | struct ls1088a_qds_mdio { |
| 79 | u8 muxval; |
| 80 | struct mii_dev *realbus; |
| 81 | }; |
| 82 | |
| 83 | static void sgmii_configure_repeater(int dpmac) |
| 84 | { |
| 85 | struct mii_dev *bus; |
| 86 | uint8_t a = 0xf; |
| 87 | int i, j, ret; |
| 88 | unsigned short value; |
| 89 | const char *dev = "LS1088A_QDS_MDIO2"; |
| 90 | int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; |
| 91 | int i2c_phy_addr = 0; |
| 92 | int phy_addr = 0; |
| 93 | |
| 94 | uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; |
| 95 | uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; |
| 96 | uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; |
| 97 | uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; |
| 98 | |
| 99 | /* Set I2c to Slot 1 */ |
| 100 | i2c_write(0x77, 0, 0, &a, 1); |
| 101 | |
| 102 | switch (dpmac) { |
| 103 | case 1: |
| 104 | i2c_phy_addr = i2c_addr[1]; |
| 105 | phy_addr = 4; |
| 106 | break; |
| 107 | case 2: |
| 108 | i2c_phy_addr = i2c_addr[0]; |
| 109 | phy_addr = 0; |
| 110 | break; |
| 111 | case 3: |
| 112 | i2c_phy_addr = i2c_addr[3]; |
| 113 | phy_addr = 0xc; |
| 114 | break; |
| 115 | case 7: |
| 116 | i2c_phy_addr = i2c_addr[2]; |
| 117 | phy_addr = 8; |
| 118 | break; |
| 119 | } |
| 120 | |
| 121 | /* Check the PHY status */ |
| 122 | ret = miiphy_set_current_dev(dev); |
| 123 | if (ret > 0) |
| 124 | goto error; |
| 125 | |
| 126 | bus = mdio_get_current_dev(); |
| 127 | debug("Reading from bus %s\n", bus->name); |
| 128 | |
| 129 | ret = miiphy_write(dev, phy_addr, 0x1f, 3); |
| 130 | if (ret > 0) |
| 131 | goto error; |
| 132 | |
| 133 | mdelay(10); |
| 134 | ret = miiphy_read(dev, phy_addr, 0x11, &value); |
| 135 | if (ret > 0) |
| 136 | goto error; |
| 137 | |
| 138 | mdelay(10); |
| 139 | |
| 140 | if ((value & 0xfff) == 0x401) { |
| 141 | miiphy_write(dev, phy_addr, 0x1f, 0); |
| 142 | printf("DPMAC %d:PHY is ..... Configured\n", dpmac); |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | for (i = 0; i < 4; i++) { |
| 147 | for (j = 0; j < 4; j++) { |
| 148 | a = 0x18; |
| 149 | i2c_write(i2c_phy_addr, 6, 1, &a, 1); |
| 150 | a = 0x38; |
| 151 | i2c_write(i2c_phy_addr, 4, 1, &a, 1); |
| 152 | a = 0x4; |
| 153 | i2c_write(i2c_phy_addr, 8, 1, &a, 1); |
| 154 | |
| 155 | i2c_write(i2c_phy_addr, 0xf, 1, |
| 156 | &ch_a_eq[i], 1); |
| 157 | i2c_write(i2c_phy_addr, 0x11, 1, |
| 158 | &ch_a_ctl2[j], 1); |
| 159 | |
| 160 | i2c_write(i2c_phy_addr, 0x16, 1, |
| 161 | &ch_b_eq[i], 1); |
| 162 | i2c_write(i2c_phy_addr, 0x18, 1, |
| 163 | &ch_b_ctl2[j], 1); |
| 164 | |
| 165 | a = 0x14; |
| 166 | i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); |
| 167 | a = 0xb5; |
| 168 | i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); |
| 169 | a = 0x20; |
| 170 | i2c_write(i2c_phy_addr, 4, 1, &a, 1); |
| 171 | mdelay(100); |
| 172 | ret = miiphy_read(dev, phy_addr, 0x11, &value); |
| 173 | if (ret > 0) |
| 174 | goto error; |
| 175 | |
| 176 | mdelay(100); |
| 177 | ret = miiphy_read(dev, phy_addr, 0x11, &value); |
| 178 | if (ret > 0) |
| 179 | goto error; |
| 180 | |
| 181 | if ((value & 0xfff) == 0x401) { |
| 182 | printf("DPMAC %d :PHY is configured ", |
| 183 | dpmac); |
| 184 | printf("after setting repeater 0x%x\n", |
| 185 | value); |
| 186 | i = 5; |
| 187 | j = 5; |
| 188 | } else { |
| 189 | printf("DPMAC %d :PHY is failed to ", |
| 190 | dpmac); |
| 191 | printf("configure the repeater 0x%x\n", value); |
| 192 | } |
| 193 | } |
| 194 | } |
| 195 | miiphy_write(dev, phy_addr, 0x1f, 0); |
| 196 | error: |
| 197 | if (ret) |
| 198 | printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac); |
| 199 | return; |
| 200 | } |
| 201 | |
| 202 | static void qsgmii_configure_repeater(int dpmac) |
| 203 | { |
| 204 | uint8_t a = 0xf; |
| 205 | int i, j; |
| 206 | int i2c_phy_addr = 0; |
| 207 | int phy_addr = 0; |
| 208 | int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; |
| 209 | |
| 210 | uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; |
| 211 | uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; |
| 212 | uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; |
| 213 | uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; |
| 214 | |
| 215 | const char *dev = mdio_names[EMI1_SLOT1]; |
| 216 | int ret = 0; |
| 217 | unsigned short value; |
| 218 | |
| 219 | /* Set I2c to Slot 1 */ |
| 220 | i2c_write(0x77, 0, 0, &a, 1); |
| 221 | |
| 222 | switch (dpmac) { |
| 223 | case 7: |
| 224 | case 8: |
| 225 | case 9: |
| 226 | case 10: |
| 227 | i2c_phy_addr = i2c_addr[2]; |
| 228 | phy_addr = 8; |
| 229 | break; |
| 230 | |
| 231 | case 3: |
| 232 | case 4: |
| 233 | case 5: |
| 234 | case 6: |
| 235 | i2c_phy_addr = i2c_addr[3]; |
| 236 | phy_addr = 0xc; |
| 237 | break; |
| 238 | } |
| 239 | |
| 240 | /* Check the PHY status */ |
| 241 | ret = miiphy_set_current_dev(dev); |
| 242 | ret = miiphy_write(dev, phy_addr, 0x1f, 3); |
| 243 | mdelay(10); |
| 244 | ret = miiphy_read(dev, phy_addr, 0x11, &value); |
| 245 | mdelay(10); |
| 246 | ret = miiphy_read(dev, phy_addr, 0x11, &value); |
| 247 | mdelay(10); |
| 248 | if ((value & 0xf) == 0xf) { |
| 249 | miiphy_write(dev, phy_addr, 0x1f, 0); |
| 250 | printf("DPMAC %d :PHY is ..... Configured\n", dpmac); |
| 251 | return; |
| 252 | } |
| 253 | |
| 254 | for (i = 0; i < 4; i++) { |
| 255 | for (j = 0; j < 4; j++) { |
| 256 | a = 0x18; |
| 257 | i2c_write(i2c_phy_addr, 6, 1, &a, 1); |
| 258 | a = 0x38; |
| 259 | i2c_write(i2c_phy_addr, 4, 1, &a, 1); |
| 260 | a = 0x4; |
| 261 | i2c_write(i2c_phy_addr, 8, 1, &a, 1); |
| 262 | |
| 263 | i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); |
| 264 | i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); |
| 265 | |
| 266 | i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); |
| 267 | i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); |
| 268 | |
| 269 | a = 0x14; |
| 270 | i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); |
| 271 | a = 0xb5; |
| 272 | i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); |
| 273 | a = 0x20; |
| 274 | i2c_write(i2c_phy_addr, 4, 1, &a, 1); |
| 275 | mdelay(100); |
| 276 | ret = miiphy_read(dev, phy_addr, 0x11, &value); |
| 277 | if (ret > 0) |
| 278 | goto error; |
| 279 | mdelay(1); |
| 280 | ret = miiphy_read(dev, phy_addr, 0x11, &value); |
| 281 | if (ret > 0) |
| 282 | goto error; |
| 283 | mdelay(10); |
| 284 | if ((value & 0xf) == 0xf) { |
| 285 | miiphy_write(dev, phy_addr, 0x1f, 0); |
| 286 | printf("DPMAC %d :PHY is ..... Configured\n", |
| 287 | dpmac); |
| 288 | return; |
| 289 | } |
| 290 | } |
| 291 | } |
| 292 | error: |
| 293 | printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac); |
| 294 | return; |
| 295 | } |
| 296 | |
| 297 | static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval) |
| 298 | { |
| 299 | return mdio_names[muxval]; |
| 300 | } |
| 301 | |
| 302 | struct mii_dev *mii_dev_for_muxval(u8 muxval) |
| 303 | { |
| 304 | struct mii_dev *bus; |
| 305 | const char *name = ls1088a_qds_mdio_name_for_muxval(muxval); |
| 306 | |
| 307 | if (!name) { |
| 308 | printf("No bus for muxval %x\n", muxval); |
| 309 | return NULL; |
| 310 | } |
| 311 | |
| 312 | bus = miiphy_get_dev_by_name(name); |
| 313 | |
| 314 | if (!bus) { |
| 315 | printf("No bus by name %s\n", name); |
| 316 | return NULL; |
| 317 | } |
| 318 | |
| 319 | return bus; |
| 320 | } |
| 321 | |
| 322 | static void ls1088a_qds_enable_SFP_TX(u8 muxval) |
| 323 | { |
| 324 | u8 brdcfg9; |
| 325 | |
| 326 | brdcfg9 = QIXIS_READ(brdcfg[9]); |
| 327 | brdcfg9 &= ~BRDCFG9_SFPTX_MASK; |
| 328 | brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT); |
| 329 | QIXIS_WRITE(brdcfg[9], brdcfg9); |
| 330 | } |
| 331 | |
| 332 | static void ls1088a_qds_mux_mdio(u8 muxval) |
| 333 | { |
| 334 | u8 brdcfg4; |
| 335 | |
| 336 | if (muxval <= 5) { |
| 337 | brdcfg4 = QIXIS_READ(brdcfg[4]); |
| 338 | brdcfg4 &= ~BRDCFG4_EMISEL_MASK; |
| 339 | brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); |
| 340 | QIXIS_WRITE(brdcfg[4], brdcfg4); |
| 341 | } |
| 342 | } |
| 343 | |
| 344 | static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr, |
| 345 | int devad, int regnum) |
| 346 | { |
| 347 | struct ls1088a_qds_mdio *priv = bus->priv; |
| 348 | |
| 349 | ls1088a_qds_mux_mdio(priv->muxval); |
| 350 | |
| 351 | return priv->realbus->read(priv->realbus, addr, devad, regnum); |
| 352 | } |
| 353 | |
| 354 | static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, |
| 355 | int regnum, u16 value) |
| 356 | { |
| 357 | struct ls1088a_qds_mdio *priv = bus->priv; |
| 358 | |
| 359 | ls1088a_qds_mux_mdio(priv->muxval); |
| 360 | |
| 361 | return priv->realbus->write(priv->realbus, addr, devad, regnum, value); |
| 362 | } |
| 363 | |
| 364 | static int ls1088a_qds_mdio_reset(struct mii_dev *bus) |
| 365 | { |
| 366 | struct ls1088a_qds_mdio *priv = bus->priv; |
| 367 | |
| 368 | return priv->realbus->reset(priv->realbus); |
| 369 | } |
| 370 | |
| 371 | static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval) |
| 372 | { |
| 373 | struct ls1088a_qds_mdio *pmdio; |
| 374 | struct mii_dev *bus = mdio_alloc(); |
| 375 | |
| 376 | if (!bus) { |
| 377 | printf("Failed to allocate ls1088a_qds MDIO bus\n"); |
| 378 | return -1; |
| 379 | } |
| 380 | |
| 381 | pmdio = malloc(sizeof(*pmdio)); |
| 382 | if (!pmdio) { |
| 383 | printf("Failed to allocate ls1088a_qds private data\n"); |
| 384 | free(bus); |
| 385 | return -1; |
| 386 | } |
| 387 | |
| 388 | bus->read = ls1088a_qds_mdio_read; |
| 389 | bus->write = ls1088a_qds_mdio_write; |
| 390 | bus->reset = ls1088a_qds_mdio_reset; |
| 391 | sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval)); |
| 392 | |
| 393 | pmdio->realbus = miiphy_get_dev_by_name(realbusname); |
| 394 | |
| 395 | if (!pmdio->realbus) { |
| 396 | printf("No bus with name %s\n", realbusname); |
| 397 | free(bus); |
| 398 | free(pmdio); |
| 399 | return -1; |
| 400 | } |
| 401 | |
| 402 | pmdio->muxval = muxval; |
| 403 | bus->priv = pmdio; |
| 404 | |
| 405 | return mdio_register(bus); |
| 406 | } |
| 407 | |
| 408 | /* |
| 409 | * Initialize the dpmac_info array. |
| 410 | * |
| 411 | */ |
| 412 | static void initialize_dpmac_to_slot(void) |
| 413 | { |
| 414 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 415 | u32 serdes1_prtcl, cfg; |
| 416 | |
| 417 | cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
| 418 | FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
| 419 | cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
| 420 | serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
| 421 | |
| 422 | switch (serdes1_prtcl) { |
| 423 | case 0x12: |
| 424 | printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
| 425 | serdes1_prtcl); |
| 426 | lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; |
| 427 | lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; |
| 428 | lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; |
| 429 | lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1; |
| 430 | break; |
| 431 | case 0x15: |
| 432 | case 0x1D: |
| 433 | printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
| 434 | serdes1_prtcl); |
| 435 | lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; |
| 436 | lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; |
| 437 | lane_to_slot_fsm1[2] = EMI_NONE; |
| 438 | lane_to_slot_fsm1[3] = EMI_NONE; |
| 439 | break; |
| 440 | case 0x1E: |
| 441 | printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
| 442 | serdes1_prtcl); |
| 443 | lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; |
| 444 | lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; |
| 445 | lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; |
| 446 | lane_to_slot_fsm1[3] = EMI_NONE; |
| 447 | break; |
| 448 | case 0x3A: |
| 449 | printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
| 450 | serdes1_prtcl); |
| 451 | lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; |
| 452 | lane_to_slot_fsm1[1] = EMI_NONE; |
| 453 | lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; |
| 454 | lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1; |
| 455 | break; |
| 456 | |
| 457 | default: |
| 458 | printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", |
| 459 | __func__, serdes1_prtcl); |
| 460 | break; |
| 461 | } |
| 462 | } |
| 463 | |
| 464 | void ls1088a_handle_phy_interface_sgmii(int dpmac_id) |
| 465 | { |
| 466 | struct mii_dev *bus; |
| 467 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 468 | u32 serdes1_prtcl, cfg; |
| 469 | |
| 470 | cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
| 471 | FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
| 472 | cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
| 473 | serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
| 474 | |
| 475 | int *riser_phy_addr; |
| 476 | char *env_hwconfig = env_get("hwconfig"); |
| 477 | |
| 478 | if (hwconfig_f("xqsgmii", env_hwconfig)) |
| 479 | riser_phy_addr = &xqsgii_riser_phy_addr[0]; |
| 480 | else |
| 481 | riser_phy_addr = &sgmii_riser_phy_addr[0]; |
| 482 | |
| 483 | switch (serdes1_prtcl) { |
| 484 | case 0x12: |
| 485 | case 0x15: |
| 486 | case 0x1E: |
| 487 | case 0x3A: |
| 488 | switch (dpmac_id) { |
| 489 | case 1: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 490 | wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]); |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 491 | break; |
| 492 | case 2: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 493 | wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]); |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 494 | break; |
| 495 | case 3: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 496 | wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]); |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 497 | break; |
| 498 | case 7: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 499 | wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]); |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 500 | break; |
| 501 | default: |
| 502 | printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id); |
| 503 | break; |
| 504 | } |
| 505 | break; |
| 506 | default: |
| 507 | printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", |
| 508 | __func__, serdes1_prtcl); |
| 509 | return; |
| 510 | } |
| 511 | dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; |
| 512 | bus = mii_dev_for_muxval(EMI1_SLOT1); |
| 513 | wriop_set_mdio(dpmac_id, bus); |
| 514 | } |
| 515 | |
| 516 | void ls1088a_handle_phy_interface_qsgmii(int dpmac_id) |
| 517 | { |
| 518 | struct mii_dev *bus; |
| 519 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 520 | u32 serdes1_prtcl, cfg; |
| 521 | |
| 522 | cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
| 523 | FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
| 524 | cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
| 525 | serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
| 526 | |
| 527 | switch (serdes1_prtcl) { |
| 528 | case 0x1D: |
| 529 | case 0x1E: |
| 530 | switch (dpmac_id) { |
| 531 | case 3: |
| 532 | case 4: |
| 533 | case 5: |
| 534 | case 6: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 535 | wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9); |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 536 | break; |
| 537 | case 7: |
| 538 | case 8: |
| 539 | case 9: |
| 540 | case 10: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 541 | wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1); |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 542 | break; |
| 543 | } |
| 544 | |
| 545 | dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; |
| 546 | bus = mii_dev_for_muxval(EMI1_SLOT1); |
| 547 | wriop_set_mdio(dpmac_id, bus); |
| 548 | break; |
| 549 | default: |
| 550 | printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", |
| 551 | serdes1_prtcl); |
| 552 | break; |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | void ls1088a_handle_phy_interface_xsgmii(int i) |
| 557 | { |
| 558 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 559 | u32 serdes1_prtcl, cfg; |
| 560 | |
| 561 | cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
| 562 | FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
| 563 | cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
| 564 | serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
| 565 | |
| 566 | switch (serdes1_prtcl) { |
| 567 | case 0x15: |
| 568 | case 0x1D: |
| 569 | case 0x1E: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 570 | wriop_set_phy_address(i, 0, i + 26); |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 571 | ls1088a_qds_enable_SFP_TX(SFP_TX); |
| 572 | break; |
| 573 | default: |
| 574 | printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", |
| 575 | serdes1_prtcl); |
| 576 | break; |
| 577 | } |
| 578 | } |
Prabhakar Kushwaha | 05f37b0 | 2017-08-31 16:37:32 +0530 | [diff] [blame] | 579 | |
| 580 | static void ls1088a_handle_phy_interface_rgmii(int dpmac_id) |
| 581 | { |
| 582 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 583 | u32 serdes1_prtcl, cfg; |
| 584 | struct mii_dev *bus; |
| 585 | |
| 586 | cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
| 587 | FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
| 588 | cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
| 589 | serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
| 590 | |
| 591 | switch (dpmac_id) { |
| 592 | case 4: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 593 | wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR); |
Prabhakar Kushwaha | 05f37b0 | 2017-08-31 16:37:32 +0530 | [diff] [blame] | 594 | dpmac_info[dpmac_id].board_mux = EMI1_RGMII1; |
| 595 | bus = mii_dev_for_muxval(EMI1_RGMII1); |
| 596 | wriop_set_mdio(dpmac_id, bus); |
| 597 | break; |
| 598 | case 5: |
Pankaj Bansal | 50adb5e | 2018-10-10 14:08:34 +0530 | [diff] [blame] | 599 | wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR); |
Prabhakar Kushwaha | 05f37b0 | 2017-08-31 16:37:32 +0530 | [diff] [blame] | 600 | dpmac_info[dpmac_id].board_mux = EMI1_RGMII2; |
| 601 | bus = mii_dev_for_muxval(EMI1_RGMII2); |
| 602 | wriop_set_mdio(dpmac_id, bus); |
| 603 | break; |
| 604 | default: |
| 605 | printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n", |
| 606 | serdes1_prtcl); |
| 607 | break; |
| 608 | } |
| 609 | } |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 610 | #endif |
| 611 | |
| 612 | int board_eth_init(bd_t *bis) |
| 613 | { |
| 614 | int error = 0, i; |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 615 | #ifdef CONFIG_FSL_MC_ENET |
| 616 | struct memac_mdio_info *memac_mdio0_info; |
| 617 | char *env_hwconfig = env_get("hwconfig"); |
| 618 | |
| 619 | initialize_dpmac_to_slot(); |
| 620 | |
| 621 | memac_mdio0_info = (struct memac_mdio_info *)malloc( |
| 622 | sizeof(struct memac_mdio_info)); |
| 623 | memac_mdio0_info->regs = |
| 624 | (struct memac_mdio_controller *) |
| 625 | CONFIG_SYS_FSL_WRIOP1_MDIO1; |
| 626 | memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME; |
| 627 | |
| 628 | /* Register the real MDIO1 bus */ |
| 629 | fm_memac_mdio_init(bis, memac_mdio0_info); |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 630 | /* Register the muxing front-ends to the MDIO buses */ |
| 631 | ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1); |
| 632 | ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2); |
| 633 | ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); |
| 634 | |
| 635 | for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { |
| 636 | switch (wriop_get_enet_if(i)) { |
Prabhakar Kushwaha | 05f37b0 | 2017-08-31 16:37:32 +0530 | [diff] [blame] | 637 | case PHY_INTERFACE_MODE_RGMII: |
Ashish Kumar | 856c9dc | 2017-10-12 15:21:54 +0530 | [diff] [blame] | 638 | case PHY_INTERFACE_MODE_RGMII_ID: |
Prabhakar Kushwaha | 05f37b0 | 2017-08-31 16:37:32 +0530 | [diff] [blame] | 639 | ls1088a_handle_phy_interface_rgmii(i); |
| 640 | break; |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 641 | case PHY_INTERFACE_MODE_QSGMII: |
| 642 | ls1088a_handle_phy_interface_qsgmii(i); |
| 643 | break; |
| 644 | case PHY_INTERFACE_MODE_SGMII: |
| 645 | ls1088a_handle_phy_interface_sgmii(i); |
| 646 | break; |
| 647 | case PHY_INTERFACE_MODE_XGMII: |
| 648 | ls1088a_handle_phy_interface_xsgmii(i); |
| 649 | break; |
| 650 | default: |
| 651 | break; |
| 652 | |
| 653 | if (i == 16) |
| 654 | i = NUM_WRIOP_PORTS; |
| 655 | } |
| 656 | } |
| 657 | |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 658 | error = cpu_eth_init(bis); |
| 659 | |
| 660 | if (hwconfig_f("xqsgmii", env_hwconfig)) { |
| 661 | for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { |
| 662 | switch (wriop_get_enet_if(i)) { |
| 663 | case PHY_INTERFACE_MODE_QSGMII: |
| 664 | qsgmii_configure_repeater(i); |
| 665 | break; |
| 666 | case PHY_INTERFACE_MODE_SGMII: |
| 667 | sgmii_configure_repeater(i); |
| 668 | break; |
| 669 | default: |
| 670 | break; |
| 671 | } |
| 672 | |
| 673 | if (i == 16) |
| 674 | i = NUM_WRIOP_PORTS; |
| 675 | } |
| 676 | } |
| 677 | #endif |
| 678 | error = pci_eth_init(bis); |
| 679 | return error; |
| 680 | } |
Bogdan Purcareata | 33ba939 | 2017-10-05 06:56:53 +0000 | [diff] [blame] | 681 | |
| 682 | #if defined(CONFIG_RESET_PHY_R) |
| 683 | void reset_phy(void) |
| 684 | { |
| 685 | mc_env_boot(); |
| 686 | } |
| 687 | #endif /* CONFIG_RESET_PHY_R */ |