blob: dfc3b1bfa5945874c45d08762afd137e768efd36 [file] [log] [blame]
Cyril Chemparathy692a7af2010-06-07 14:13:32 -04001/*
2 * TNETV107X: Clock APIs
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Cyril Chemparathy692a7af2010-06-07 14:13:32 -04005 */
6
7#ifndef __ASM_ARCH_CLOCK_H
8#define __ASM_ARCH_CLOCK_H
9
10#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0
11#define PSC_MDCTL_NEXT_SYNCRST 0x1
12#define PSC_MDCTL_NEXT_DISABLE 0x2
13#define PSC_MDCTL_NEXT_ENABLE 0x3
14
15#define CONFIG_SYS_INT_OSC_FREQ 24000000
16
17#ifndef __ASSEMBLY__
18
19/* PLL identifiers */
20enum pll_type_e {
21 SYS_PLL,
22 TDM_PLL,
23 ETH_PLL
24};
25
26/* PLL configuration data */
27struct pll_init_data {
28 int pll;
29 int internal_osc;
30 unsigned long pll_freq;
31 unsigned long div_freq[10];
32};
33
34void init_plls(int num_pll, struct pll_init_data *config);
35int lpsc_status(unsigned int mod);
36void lpsc_control(int mod, unsigned long state, int lrstz);
37unsigned long clk_get_rate(unsigned int clk);
38unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
39int clk_set_rate(unsigned int clk, unsigned long hz);
40
41static inline void clk_enable(unsigned int mod)
42{
43 lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
44}
45
46static inline void clk_disable(unsigned int mod)
47{
48 lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
49}
50
51#endif
52
53#endif