Tuomas Tynkkynen | 28cac52 | 2017-09-19 23:18:07 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017 Tuomas Tynkkynen |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | #include <common.h> |
| 7 | #include <fdtdec.h> |
| 8 | |
Tuomas Tynkkynen | dfdd46d | 2018-01-11 16:11:23 +0200 | [diff] [blame^] | 9 | #ifdef CONFIG_ARM64 |
| 10 | #include <asm/armv8/mmu.h> |
| 11 | |
| 12 | static struct mm_region qemu_arm64_mem_map[] = { |
| 13 | { |
| 14 | /* Flash */ |
| 15 | .virt = 0x00000000UL, |
| 16 | .phys = 0x00000000UL, |
| 17 | .size = 0x08000000UL, |
| 18 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 19 | PTE_BLOCK_INNER_SHARE |
| 20 | }, { |
| 21 | /* Peripherals */ |
| 22 | .virt = 0x08000000UL, |
| 23 | .phys = 0x08000000UL, |
| 24 | .size = 0x38000000, |
| 25 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 26 | PTE_BLOCK_NON_SHARE | |
| 27 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 28 | }, { |
| 29 | /* RAM */ |
| 30 | .virt = 0x40000000UL, |
| 31 | .phys = 0x40000000UL, |
| 32 | .size = 0xc0000000UL, |
| 33 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 34 | PTE_BLOCK_INNER_SHARE |
| 35 | }, { |
| 36 | /* List terminator */ |
| 37 | 0, |
| 38 | } |
| 39 | }; |
| 40 | |
| 41 | struct mm_region *mem_map = qemu_arm64_mem_map; |
| 42 | #endif |
| 43 | |
Tuomas Tynkkynen | 28cac52 | 2017-09-19 23:18:07 +0300 | [diff] [blame] | 44 | int board_init(void) |
| 45 | { |
| 46 | return 0; |
| 47 | } |
| 48 | |
| 49 | int dram_init(void) |
| 50 | { |
| 51 | if (fdtdec_setup_memory_size() != 0) |
| 52 | return -EINVAL; |
| 53 | |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | int dram_init_banksize(void) |
| 58 | { |
| 59 | fdtdec_setup_memory_banksize(); |
| 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | void *board_fdt_blob_setup(void) |
| 65 | { |
| 66 | /* QEMU loads a generated DTB for us at the start of RAM. */ |
| 67 | return (void *)CONFIG_SYS_SDRAM_BASE; |
| 68 | } |