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git01.mediatek.com / filogic / uboot / df6a2158981f0a71379e99f4e465dee88c40605e / . / include / configs / gardena-smart-gateway-mt7688.h
blob: a1400eba1adab12d47c34e716d1db6a559b6f9ff [file] [log] [blame]
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4 */
5
6#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H
7#define __CONFIG_GARDENA_SMART_GATEWAY_H
8
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]9/* RAM */
10#define CONFIG_SYS_SDRAM_BASE 0x80000000
11
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]12#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
13
developer9720bc32020-04-21 09:28:48 +0200[diff] [blame]14/* SPL */
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]15
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]16#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
developer9720bc32020-04-21 09:28:48 +0200[diff] [blame]17
18/* Dummy value */
19#define CONFIG_SYS_UBOOT_BASE 0
20
21/* Serial SPL */
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]22#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Tom Rinidf6a2152022-11-16 13:10:28 -0500[diff] [blame^]23#define CFG_SYS_NS16550_CLK 40000000
24#define CFG_SYS_NS16550_COM1 0xb0000c00
developer9720bc32020-04-21 09:28:48 +0200[diff] [blame]25#endif
26
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]27/* UART */
28#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
developere1693432019-09-25 17:45:42 +0800[diff] [blame]29 230400, 460800, 921600 }
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]30
31/* RAM */
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]32
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]33/* Environment settings */
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]34
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]35#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */