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git01.mediatek.com / filogic / uboot / df477acea01263894be6e6131cb57c92a4e9d723 / . / include / configs / vl_ma2sc.h
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esw@bus-elektronik.de4ecc4272012-01-16 00:22:02 +0000[diff] [blame]1/*
2 * (C) Copyright 2009-2012
3 * Jens Scharsig <esw@bus-elekronik.de>
4 * BuS Elektronik GmbH & Co. KG
5 *
6 * Configuation settings for the VL_MA2SC board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*--------------------------------------------------------------------------*/
31
esw@bus-elektronik.de4ecc4272012-01-16 00:22:02 +0000[diff] [blame]32#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */
33#define CONFIG_AT91FAMILY
34#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
35#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
36#define CONFIG_ARCH_CPU_INIT
37#define CONFIG_MISC_INIT_R
38
39#include <asm/hardware.h>
40
41#define MACH_TYPE_VL_MA2SC 2412
42#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
43
44#define CONFIG_SYS_DCACHE_OFF
45
46#ifdef CONFIG_RAMLOAD
47#define CONFIG_SYS_TEXT_BASE 0x21000000
48#else
49#define CONFIG_SYS_TEXT_BASE 0x00000000
50#endif
51#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
52
53#define CONFIG_IDENT_STRING " on MiS Activ 2"
54#define CONFIG_VERSION_VARIABLE
55#define CONFIG_AT91_GPIO
56
57#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
58#define CONFIG_SYS_USE_NORFLASH
59#define CONFIG_SYS_USE_BOOT_NORFLASH
60#endif
61
62#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
63#define CONFIG_SETUP_MEMORY_TAGS
64#define CONFIG_INITRD_TAG
65
66#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
67#define CONFIG_SKIP_LOWLEVEL_INIT
68#endif
69
70/*
71 * Hardware drivers
72 */
73
74#define CONFIG_BOARD_EARLY_INIT_F
75
76#define CONFIG_WATCHDOG
77
78#define CONFIG_ATMEL_USART
79#define CONFIG_USART_BASE ATMEL_BASE_DBGU
80#define CONFIG_USART_ID ATMEL_ID_SYS
81
82/* LCD */
83#define CONFIG_LCD
84#define CONFIG_ATMEL_LCD
85#define CONFIG_SPLASH_SCREEN
86#define CONFIG_SYS_BLACK_ON_WHITE
87#define LCD_BPP LCD_COLOR8
88#define CONFIG_ATMEL_LCD_BGR555
89
90#define CONFIG_SYS_CONSOLE_IS_IN_ENV
91#define CONFIG_BOOTDELAY 3
92
93/*
94 * BOOTP options
95 */
96#define CONFIG_BOOTP_BOOTFILESIZE
97#define CONFIG_BOOTP_BOOTPATH
98#define CONFIG_BOOTP_GATEWAY
99#define CONFIG_BOOTP_HOSTNAME
100
101/*
102 * Command line configuration.
103 */
104#include <config_cmd_default.h>
105#undef CONFIG_CMD_BDI
106#undef CONFIG_CMD_FPGA
107#undef CONFIG_CMD_IMI
108#undef CONFIG_CMD_LOADS
109
110#define CONFIG_CMD_BMP
111#define CONFIG_CMD_DATE
112#define CONFIG_CMD_DHCP
113#define CONFIG_CMD_I2C
114#define CONFIG_CMD_NAND
115#define CONFIG_CMD_MII
116#define CONFIG_CMD_PING
117#define CONFIG_CMD_MD5SUM
118#define CONFIG_CMD_SHA1SUM
119/*
120#define CONFIG_CMD_SPI
121*/
122#define CONFIG_CMD_FAT
123#define CONFIG_CMD_USB
124
125#define CONFIG_SYS_LONGHELP
126#define CONFIG_MD5
127#define CONFIG_SHA1
128
129/*----------------------------------------------------------------------------
130 * Hardware confuguration
131 *---------------------------------------------------------------------------*/
132
133/* USB */
134#define CONFIG_USB_ATMEL
135#define CONFIG_USB_OHCI_NEW
136#define CONFIG_DOS_PARTITION
137#define CONFIG_SYS_USB_OHCI_CPU_INIT
138#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
139#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
140#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
141#define CONFIG_USB_STORAGE
142#define CONFIG_AT91C_PQFP_UHPBUG
143
144/* I2C-Bus */
145
146#define CONFIG_SYS_I2C_SPEED 50000
147#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
148
149#ifndef CONFIG_HARD_I2C
150#define CONFIG_SOFT_I2C
151
152/* Software I2C driver configuration */
153
154#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
155
156#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
157#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
158
159#define I2C_INIT i2c_init_board();
160#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
161#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
162#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
163#define I2C_SDA(bit) \
164 do { \
165 if (bit) \
166 writel(AT91_PIN_SDA, &pio->piob.sodr); \
167 else \
168 writel(AT91_PIN_SDA, &pio->piob.codr); \
169 } while (0);
170#define I2C_SCL(bit) \
171 do { \
172 if (bit) \
173 writel(AT91_PIN_SCL, &pio->piob.sodr); \
174 else \
175 writel(AT91_PIN_SCL, &pio->piob.codr); \
176 } while (0);
177#endif
178
179/* I2C-RTC */
180
181#ifdef CONFIG_CMD_DATE
182#define CONFIG_RTC_DS1338
183#define CONFIG_SYS_I2C_RTC_ADDR 0x68
184#endif
185
186/* EEPROM */
187
188#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
189#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
190
191/* define PDC[31:16] as DATA[31:16] */
192#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
193#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
194
195/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
196#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
197 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
198 AT91_MATRIX_CSA_EBI_CS1A)
199
200/* user reset enable */
201#define CONFIG_SYS_RSTC_RMR_VAL \
202 (AT91_RSTC_KEY | \
203 AT91_RSTC_MR_URSTEN | \
204 AT91_RSTC_MR_ERSTL(15))
205
206/* Disable Watchdog */
207#define CONFIG_SYS_WDTC_WDMR_VAL \
208 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
209 AT91_WDT_MR_WDV(0xFFF) | \
210 AT91_WDT_MR_WDDIS | \
211 AT91_WDT_MR_WDD(0xFFF))
212
213/* clocks */
214
215#define CONFIG_SYS_HZ 1000
216#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
217
218#define MHZ180
219#if defined(MHZ199)
220/* 199,8994 MHZ */
221#define MASTER_PLL_MUL 911
222#define MASTER_PLL_DIV 56
223#define MASTER_PLL_OUT 2
224#elif defined(MHZ180)
225/* 180 MHZ */
226#define MASTER_PLL_MUL 1875
227#define MASTER_PLL_DIV 128
228#define MASTER_PLL_OUT 2
229#elif defined(MHZTEST)
230/* Test MHZ */
231#define CONFIG_DISPLAY_CPUINFO
232#define MASTER_PLL_MUL 8
233#define MASTER_PLL_DIV 1
234#define MASTER_PLL_OUT 2
235#else
236/* 176.9472 MHZ */
237#define MASTER_PLL_MUL 72
238#define MASTER_PLL_DIV 5
239#define MASTER_PLL_OUT 2
240#endif
241
242#define CONFIG_SYS_MOR_VAL \
243 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
244
245#define CONFIG_SYS_PLLAR_VAL \
246 (AT91_PMC_PLLAR_29 | \
247 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
248 AT91_PMC_PLLXR_PLLCOUNT(63) | \
249 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
250 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
251
252/* PCK/2 = MCK Master Clock from PLLA */
253#define CONFIG_SYS_MCKR1_VAL \
254 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
255 AT91_PMC_MCKR_MDIV_2)
256
257/* PCK/2 = MCK Master Clock from PLLA */
258#define CONFIG_SYS_MCKR2_VAL \
259 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
260 AT91_PMC_MCKR_MDIV_2)
261
262/* SDRAM */
263#define CONFIG_NR_DRAM_BANKS 1
264#define CONFIG_SYS_SDRAM_BASE 0x20000000
265#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
266#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
267
268#define CONFIG_SYS_SDRC_MR_VAL1 0
269#define CONFIG_SYS_SDRC_TR_VAL1 700
270#define CONFIG_SYS_SDRC_CR_VAL \
271 (AT91_SDRAMC_NC_9 | \
272 AT91_SDRAMC_NR_13 | \
273 AT91_SDRAMC_NB_4 | \
274 AT91_SDRAMC_CAS_3 | \
275 AT91_SDRAMC_DBW_32 | \
276 (2 << 8) | /* Write Recovery Delay */ \
277 (7 << 12) | /* Row Cycle Delay */ \
278 (2 << 16) | /* Row Precharge Delay */ \
279 (2 << 20) | /* Row to Column Delay */ \
280 (5 << 24) | /* Active to Precharge Delay */ \
281 (8 << 28)) /* Exit Self Refresh to Active Delay */
282
283#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
284#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
285#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
286#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
287#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
288#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
289#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
290#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
291#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
292#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
293#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
294#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
295#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
296#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
297#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
298#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
299#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
300#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
301
302/* NOR flash */
303
304#define CONFIG_FLASH_SHOW_PROGRESS 45
305#define CONFIG_SYS_FLASH_CFI
306#define CONFIG_FLASH_CFI_DRIVER
307#define PHYS_FLASH_1 0x10000000
308#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
309#define CONFIG_SYS_MAX_FLASH_SECT 256
310#define CONFIG_SYS_MAX_FLASH_BANKS 1
311
312#define CONFIG_ENV_IS_IN_FLASH
313#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
314
315/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
316#define CONFIG_SYS_SMC0_SETUP0_VAL \
317 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
318 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
319#define CONFIG_SYS_SMC0_PULSE0_VAL \
320 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
321 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
322#define CONFIG_SYS_SMC0_CYCLE0_VAL \
323 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
324#define CONFIG_SYS_SMC0_MODE0_VAL \
325 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
326 AT91_SMC_MODE_DBW_16 | \
327 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
328
329/* NAND flash */
330#ifdef CONFIG_CMD_NAND
331#define CONFIG_NAND_ATMEL
332#define CONFIG_SYS_MAX_NAND_DEVICE 1
333#define CONFIG_SYS_NAND_BASE 0x40000000
334#define CONFIG_SYS_NAND_DBW_8 1
335#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
336#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
337#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
338#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0
339#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
340#endif
341
342/* Ethernet */
343#define CONFIG_MACB
344#define CONFIG_RMII
345#define CONFIG_NET_MULTI
346#define CONFIG_NET_RETRY_COUNT 5
347
348#define CONFIG_OVERWRITE_ETHADDR_ONCE
349
350#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
351
352#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
353#define CONFIG_SYS_MEMTEST_END 0x21e00000
354
355/* Address and size of Primary Environment Sector */
356#ifdef CONFIG_ENV_IS_IN_FLASH
357#define CONFIG_ENV_SIZE 0x20000
358#else
359#define CONFIG_ENV_SIZE 0x2000
360#endif
361
362#define CONFIG_BAUDRATE 115200
363#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
364 38400, 57600, 9600 }
365
366#define CONFIG_SYS_PROMPT "U-Boot> "
367#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
368#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
369#define CONFIG_SYS_PBSIZE \
370 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
371#define CONFIG_CMDLINE_EDITING
372#define CONFIG_AUTO_COMPLETE
373
374/*
375 * Size of malloc() pool
376 */
377#define CONFIG_SYS_MALLOC_LEN \
378 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
379#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
380
esw@bus-elektronik.de4ecc4272012-01-16 00:22:02 +0000[diff] [blame]381#ifndef CONFIG_RAMLOAD
382#define CONFIG_BOOTCOMMAND "run nfsboot"
383#endif
384#define CONFIG_BOOT_RETRY_TIME -1
385#define CONFIG_BOOT_RETRY_MIN 15
386
387#define CONFIG_NFSBOOTCOMMAND \
388 "dhcp $(copy_addr) $(kernelname);" \
389 "run bootargsdefaults;" \
390 "set bootargs $(bootargs) boot=nfs " \
391 ";echo $(bootargs)" \
392 ";bootm"
393
394#define CONFIG_EXTRA_ENV_SETTINGS \
395 "ubootaddr=10000000\0" \
396 "splashimage=10080000\0" \
397 "kerneladdr=100A0000\0" \
398 "kernelsize=00800000\0" \
399 "minifsaddr=108A0000\0" \
400 "minifssize=00060000\0" \
401 "rootfsaddr=10900000\0" \
402 "copy_addr=20200000\0" \
403 "rootfssize=01700000\0" \
404 "kernelname=uImage_vl_ma2sc\0" \
405 "bootargsdefaults=set bootargs " \
406 "console=ttyS0,115200 " \
407 "video=atmel_lcdfb " \
408 "mem=62M " \
409 "panic=10 " \
410 "boardrevison=\\\"${revision}\\\" " \
411 "uboot=\\\"${ver}\\\" " \
412 "\0" \
413 "update_all=run update_kernel;run update_root;" \
414 "run update_splash; run update_uboot\0" \
415 "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
416 "dhcp $(copy_addr) $(kernelname);" \
417 "erase $(kerneladdr) +$(kernelsize);" \
418 "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
419 "protect on $(kerneladdr) +$(kernelsize)" \
420 "\0" \
421 "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
422 "dhcp $(copy_addr) vl_ma2sc.root;" \
423 "erase $(rootfsaddr) +$(rootfssize);" \
424 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
425 "\0" \
426 "update_splash=protect off $(splashimage) +20000;" \
427 "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
428 "erase $(splashimage) +20000;" \
429 "cp.b $(fileaddr) 10080000 $(filesize);" \
430 "protect on $(splashimage) +20000\0" \
431 "update_uboot=protect off 10000000 1005FFFF;" \
432 "dhcp $(copy_addr) u-boot_vl_ma2sc;" \
433 "erase 10000000 1005FFFF;" \
434 "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
435 "protect on 10000000 1005FFFF;reset\0" \
436 "emergency=run bootargsdefaults;" \
437 "set bootargs $(bootargs) root=initramfs boot=emergency " \
438 ";bootm $(kerneladdr)\0" \
439 "netemergency=run bootargsdefaults;" \
440 "dhcp $(copy_addr) $(kernelname);" \
441 "set bootargs $(bootargs) root=initramfs boot=emergency " \
442 ";bootm $(copy_addr)\0" \
443 "norboot=run bootargsdefaults;" \
444 "set bootargs $(bootargs) root=initramfs boot=local quiet " \
445 ";bootm $(kerneladdr)\0" \
446 "nandboot=run bootargsdefaults;" \
447 "set bootargs $(bootargs) root=initramfs boot=nand " \
448 ";bootm $(kerneladdr)\0" \
449 "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
450 "clearenv=protect off 10060000 1007FFFF;" \
451 "erase 10060000 1007FFFF;reset\0" \
452 " "
453
esw@bus-elektronik.de4ecc4272012-01-16 00:22:02 +0000[diff] [blame]454#endif