Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 6 | #include <dm.h> |
| 7 | #include <log.h> |
| 8 | #include <tpm_api.h> |
| 9 | #include <tpm-v1.h> |
| 10 | #include <tpm-v2.h> |
| 11 | #include <tpm_api.h> |
| 12 | |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 13 | u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode) |
| 14 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 15 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 16 | return tpm1_startup(dev, mode); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 17 | } else if (tpm_is_v2(dev)) { |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 18 | enum tpm2_startup_types type; |
| 19 | |
| 20 | switch (mode) { |
| 21 | case TPM_ST_CLEAR: |
| 22 | type = TPM2_SU_CLEAR; |
| 23 | break; |
| 24 | case TPM_ST_STATE: |
| 25 | type = TPM2_SU_STATE; |
| 26 | break; |
| 27 | default: |
| 28 | case TPM_ST_DEACTIVATED: |
| 29 | return -EINVAL; |
| 30 | } |
| 31 | return tpm2_startup(dev, type); |
| 32 | } else { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 33 | return -ENOSYS; |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 34 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 35 | } |
| 36 | |
Ilias Apalodimas | 42d7bdf | 2023-01-25 12:18:36 +0200 | [diff] [blame] | 37 | u32 tpm_auto_start(struct udevice *dev) |
| 38 | { |
Simon Glass | 3467ed2 | 2023-02-21 06:24:52 -0700 | [diff] [blame] | 39 | u32 rc; |
Ilias Apalodimas | 42d7bdf | 2023-01-25 12:18:36 +0200 | [diff] [blame] | 40 | |
Simon Glass | 3467ed2 | 2023-02-21 06:24:52 -0700 | [diff] [blame] | 41 | /* |
| 42 | * the tpm_init() will return -EBUSY if the init has already happened |
| 43 | * The selftest and startup code can run multiple times with no side |
| 44 | * effects |
| 45 | */ |
| 46 | rc = tpm_init(dev); |
| 47 | if (rc && rc != -EBUSY) |
| 48 | return rc; |
| 49 | |
| 50 | if (tpm_is_v1(dev)) |
| 51 | return tpm1_auto_start(dev); |
| 52 | else if (tpm_is_v2(dev)) |
| 53 | return tpm2_auto_start(dev); |
| 54 | else |
| 55 | return -ENOSYS; |
Ilias Apalodimas | 42d7bdf | 2023-01-25 12:18:36 +0200 | [diff] [blame] | 56 | } |
| 57 | |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 58 | u32 tpm_resume(struct udevice *dev) |
| 59 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 60 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 61 | return tpm1_startup(dev, TPM_ST_STATE); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 62 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 63 | return tpm2_startup(dev, TPM2_SU_STATE); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 64 | else |
| 65 | return -ENOSYS; |
| 66 | } |
| 67 | |
| 68 | u32 tpm_self_test_full(struct udevice *dev) |
| 69 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 70 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 71 | return tpm1_self_test_full(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 72 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 73 | return tpm2_self_test(dev, TPMI_YES); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 74 | else |
| 75 | return -ENOSYS; |
| 76 | } |
| 77 | |
| 78 | u32 tpm_continue_self_test(struct udevice *dev) |
| 79 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 80 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 81 | return tpm1_continue_self_test(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 82 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 83 | return tpm2_self_test(dev, TPMI_NO); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 84 | else |
| 85 | return -ENOSYS; |
| 86 | } |
| 87 | |
| 88 | u32 tpm_clear_and_reenable(struct udevice *dev) |
| 89 | { |
| 90 | u32 ret; |
| 91 | |
| 92 | log_info("TPM: Clear and re-enable\n"); |
| 93 | ret = tpm_force_clear(dev); |
| 94 | if (ret != TPM_SUCCESS) { |
| 95 | log_err("Can't initiate a force clear\n"); |
| 96 | return ret; |
| 97 | } |
| 98 | |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 99 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 100 | ret = tpm1_physical_enable(dev); |
| 101 | if (ret != TPM_SUCCESS) { |
| 102 | log_err("TPM: Can't set enabled state\n"); |
| 103 | return ret; |
| 104 | } |
| 105 | |
| 106 | ret = tpm1_physical_set_deactivated(dev, 0); |
| 107 | if (ret != TPM_SUCCESS) { |
| 108 | log_err("TPM: Can't set deactivated state\n"); |
| 109 | return ret; |
| 110 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | return TPM_SUCCESS; |
| 114 | } |
| 115 | |
| 116 | u32 tpm_nv_enable_locking(struct udevice *dev) |
| 117 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 118 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 119 | return tpm1_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 120 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 121 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 122 | else |
| 123 | return -ENOSYS; |
| 124 | } |
| 125 | |
| 126 | u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count) |
| 127 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 128 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 129 | return tpm1_nv_read_value(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 130 | else if (tpm_is_v2(dev)) |
Simon Glass | 3d930ed | 2021-02-06 14:23:40 -0700 | [diff] [blame] | 131 | return tpm2_nv_read_value(dev, index, data, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 132 | else |
| 133 | return -ENOSYS; |
| 134 | } |
| 135 | |
| 136 | u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data, |
| 137 | u32 count) |
| 138 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 139 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 140 | return tpm1_nv_write_value(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 141 | else if (tpm_is_v2(dev)) |
Simon Glass | 3d930ed | 2021-02-06 14:23:40 -0700 | [diff] [blame] | 142 | return tpm2_nv_write_value(dev, index, data, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 143 | else |
| 144 | return -ENOSYS; |
| 145 | } |
| 146 | |
| 147 | u32 tpm_set_global_lock(struct udevice *dev) |
| 148 | { |
| 149 | return tpm_nv_write_value(dev, TPM_NV_INDEX_0, NULL, 0); |
| 150 | } |
| 151 | |
| 152 | u32 tpm_write_lock(struct udevice *dev, u32 index) |
| 153 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 154 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 155 | return -ENOSYS; |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 156 | else if (tpm_is_v2(dev)) |
Simon Glass | e9d3d59 | 2021-02-06 14:23:41 -0700 | [diff] [blame] | 157 | return tpm2_write_lock(dev, index); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 158 | else |
| 159 | return -ENOSYS; |
| 160 | } |
| 161 | |
| 162 | u32 tpm_pcr_extend(struct udevice *dev, u32 index, const void *in_digest, |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 163 | uint size, void *out_digest, const char *name) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 164 | { |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 165 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 166 | return tpm1_extend(dev, index, in_digest, out_digest); |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 167 | } else if (tpm_is_v2(dev)) { |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 168 | return tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, in_digest, |
| 169 | TPM2_DIGEST_LEN); |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 170 | /* @name is ignored as we do not support the TPM log here */ |
| 171 | } else { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 172 | return -ENOSYS; |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 173 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count) |
| 177 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 178 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 179 | return tpm1_pcr_read(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 180 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 181 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 182 | else |
| 183 | return -ENOSYS; |
| 184 | } |
| 185 | |
| 186 | u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence) |
| 187 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 188 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 189 | return tpm1_tsc_physical_presence(dev, presence); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 190 | |
| 191 | /* |
| 192 | * Nothing to do on TPM2 for this; use platform hierarchy availability |
| 193 | * instead. |
| 194 | */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 195 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 196 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 197 | else |
| 198 | return -ENOSYS; |
| 199 | } |
| 200 | |
| 201 | u32 tpm_finalise_physical_presence(struct udevice *dev) |
| 202 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 203 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 204 | return tpm1_finalise_physical_presence(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 205 | |
| 206 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 207 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 208 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 209 | else |
| 210 | return -ENOSYS; |
| 211 | } |
| 212 | |
| 213 | u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count) |
| 214 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 215 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 216 | return tpm1_read_pubek(dev, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 217 | else if (tpm_is_v2(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 218 | return -ENOSYS; /* not implemented yet */ |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 219 | else |
| 220 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | u32 tpm_force_clear(struct udevice *dev) |
| 224 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 225 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 226 | return tpm1_force_clear(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 227 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 228 | return tpm2_clear(dev, TPM2_RH_PLATFORM, NULL, 0); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 229 | else |
| 230 | return -ENOSYS; |
| 231 | } |
| 232 | |
| 233 | u32 tpm_physical_enable(struct udevice *dev) |
| 234 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 235 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 236 | return tpm1_physical_enable(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 237 | |
| 238 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 239 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 240 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 241 | else |
| 242 | return -ENOSYS; |
| 243 | } |
| 244 | |
| 245 | u32 tpm_physical_disable(struct udevice *dev) |
| 246 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 247 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 248 | return tpm1_physical_disable(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 249 | |
| 250 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 251 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 252 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 253 | else |
| 254 | return -ENOSYS; |
| 255 | } |
| 256 | |
| 257 | u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state) |
| 258 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 259 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 260 | return tpm1_physical_set_deactivated(dev, state); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 261 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 262 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 263 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 264 | else |
| 265 | return -ENOSYS; |
| 266 | } |
| 267 | |
| 268 | u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap, |
| 269 | void *cap, size_t count) |
| 270 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 271 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 272 | return tpm1_get_capability(dev, cap_area, sub_cap, cap, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 273 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 274 | return tpm2_get_capability(dev, cap_area, sub_cap, cap, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 275 | else |
| 276 | return -ENOSYS; |
| 277 | } |
| 278 | |
| 279 | u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm) |
| 280 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 281 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 282 | return tpm1_get_permissions(dev, index, perm); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 283 | else if (tpm_is_v2(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 284 | return -ENOSYS; /* not implemented yet */ |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 285 | else |
| 286 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | u32 tpm_get_random(struct udevice *dev, void *data, u32 count) |
| 290 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 291 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 292 | return tpm1_get_random(dev, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 293 | else if (tpm_is_v2(dev)) |
Sughosh Ganu | 9737fab | 2022-07-22 21:32:04 +0530 | [diff] [blame] | 294 | return tpm2_get_random(dev, data, count); |
| 295 | |
| 296 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 297 | } |