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wdenk9c53f402003-10-15 23:53:47 +00001/*
Andy Flemingf08233c2007-08-14 01:34:21 -05002 * Copyright 2004, 2007 Freescale Semiconductor.
wdenk9c53f402003-10-15 23:53:47 +00003 * Copyright(c) 2003 Motorola Inc.
wdenk9c53f402003-10-15 23:53:47 +00004 */
5
6#ifndef __MPC85xx_H__
7#define __MPC85xx_H__
8
Tom Rinidec7ea02024-05-20 13:35:03 -06009#include <config.h>
wdenk9c53f402003-10-15 23:53:47 +000010#if defined(CONFIG_E500)
11#include <e500.h>
12#endif
13
wdenk13eb2212004-07-09 23:27:13 +000014/*
15 * SCCR - System Clock Control Register, 9-8
wdenk9c53f402003-10-15 23:53:47 +000016 */
wdenk13eb2212004-07-09 23:27:13 +000017#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
18#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
wdenk9c53f402003-10-15 23:53:47 +000019#define SCCR_DFBRG_SHIFT 0
20
wdenk13eb2212004-07-09 23:27:13 +000021#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
22#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
23#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
24#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
wdenk9c53f402003-10-15 23:53:47 +000025
Timur Tabid8f341c2011-08-04 18:03:41 -050026/*
27 * Define default values for some CCSR macros to make header files cleaner*
28 *
29 * To completely disable CCSR relocation in a board header file, define
Tom Rini6a5dccc2022-11-16 13:10:41 -050030 * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS
31 * to a value that is the same as CFG_SYS_CCSRBAR.
Timur Tabid8f341c2011-08-04 18:03:41 -050032 */
33
Tom Rini6a5dccc2022-11-16 13:10:41 -050034#ifdef CFG_SYS_CCSRBAR_PHYS
35#error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \
36CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead."
Timur Tabid8f341c2011-08-04 18:03:41 -050037#endif
38
Tom Rini17845c52022-05-21 11:26:27 -040039#if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE)
Tom Rini6a5dccc2022-11-16 13:10:41 -050040#undef CFG_SYS_CCSRBAR_PHYS_HIGH
41#undef CFG_SYS_CCSRBAR_PHYS_LOW
42#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
Timur Tabid8f341c2011-08-04 18:03:41 -050043#endif
44
Tom Rini6a5dccc2022-11-16 13:10:41 -050045#ifndef CFG_SYS_CCSRBAR
46#define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
Timur Tabid8f341c2011-08-04 18:03:41 -050047#endif
48
Tom Rini6a5dccc2022-11-16 13:10:41 -050049#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
Timur Tabid8f341c2011-08-04 18:03:41 -050050#ifdef CONFIG_PHYS_64BIT
Tom Rini6a5dccc2022-11-16 13:10:41 -050051#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
Timur Tabid8f341c2011-08-04 18:03:41 -050052#else
Tom Rini6a5dccc2022-11-16 13:10:41 -050053#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
Timur Tabid8f341c2011-08-04 18:03:41 -050054#endif
55#endif
56
Tom Rini6a5dccc2022-11-16 13:10:41 -050057#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
58#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
Timur Tabid8f341c2011-08-04 18:03:41 -050059#endif
60
Tom Rini6a5dccc2022-11-16 13:10:41 -050061#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
62 CFG_SYS_CCSRBAR_PHYS_LOW)
Timur Tabid8f341c2011-08-04 18:03:41 -050063
wdenk9c53f402003-10-15 23:53:47 +000064#endif /* __MPC85xx_H__ */