| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> |
| 4 | * |
| 5 | * X-Powers AXP818 Power Management IC driver |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #define AXP818_CHIP_ID 0x03 |
| 9 | |
| 10 | #define AXP818_OUTPUT_CTRL1 0x10 |
| 11 | #define AXP818_OUTPUT_CTRL1_DCDC1_EN (1 << 0) |
| 12 | #define AXP818_OUTPUT_CTRL1_DCDC2_EN (1 << 1) |
| 13 | #define AXP818_OUTPUT_CTRL1_DCDC3_EN (1 << 2) |
| 14 | #define AXP818_OUTPUT_CTRL1_DCDC4_EN (1 << 3) |
| 15 | #define AXP818_OUTPUT_CTRL1_DCDC5_EN (1 << 4) |
| 16 | #define AXP818_OUTPUT_CTRL1_DCDC6_EN (1 << 5) |
| 17 | #define AXP818_OUTPUT_CTRL1_DCDC7_EN (1 << 6) |
| 18 | #define AXP818_OUTPUT_CTRL2 0x12 |
| 19 | #define AXP818_OUTPUT_CTRL2_ELDO1_EN (1 << 0) |
| 20 | #define AXP818_OUTPUT_CTRL2_ELDO2_EN (1 << 1) |
| 21 | #define AXP818_OUTPUT_CTRL2_ELDO3_EN (1 << 2) |
| 22 | #define AXP818_OUTPUT_CTRL2_DLDO1_EN (1 << 3) |
| 23 | #define AXP818_OUTPUT_CTRL2_DLDO2_EN (1 << 4) |
| 24 | #define AXP818_OUTPUT_CTRL2_DLDO3_EN (1 << 5) |
| 25 | #define AXP818_OUTPUT_CTRL2_DLDO4_EN (1 << 6) |
| Chen-Yu Tsai | 0e3efd3 | 2016-05-02 10:28:12 +0800 | [diff] [blame] | 26 | #define AXP818_OUTPUT_CTRL2_SW_EN (1 << 7) |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 27 | #define AXP818_OUTPUT_CTRL3 0x13 |
| 28 | #define AXP818_OUTPUT_CTRL3_FLDO1_EN (1 << 2) |
| 29 | #define AXP818_OUTPUT_CTRL3_FLDO2_EN (1 << 3) |
| 30 | #define AXP818_OUTPUT_CTRL3_FLDO3_EN (1 << 4) |
| 31 | #define AXP818_OUTPUT_CTRL3_ALDO1_EN (1 << 5) |
| 32 | #define AXP818_OUTPUT_CTRL3_ALDO2_EN (1 << 6) |
| 33 | #define AXP818_OUTPUT_CTRL3_ALDO3_EN (1 << 7) |
| 34 | |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 35 | #define AXP818_DLDO1_CTRL 0x15 |
| 36 | #define AXP818_DLDO2_CTRL 0x16 |
| 37 | #define AXP818_DLDO3_CTRL 0x17 |
| 38 | #define AXP818_DLDO4_CTRL 0x18 |
| 39 | #define AXP818_ELDO1_CTRL 0x19 |
| 40 | #define AXP818_ELDO2_CTRL 0x1a |
| 41 | #define AXP818_ELDO3_CTRL 0x1b |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 42 | #define AXP818_FLDO1_CTRL 0x1c |
| 43 | #define AXP818_FLDO2_3_CTRL 0x1d |
| Chen-Yu Tsai | d028fba | 2016-03-30 00:26:48 +0800 | [diff] [blame] | 44 | #define AXP818_FLDO2_3_CTRL_FLDO3_VOL (1 << 4) |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 45 | #define AXP818_DCDC1_CTRL 0x20 |
| 46 | #define AXP818_DCDC2_CTRL 0x21 |
| 47 | #define AXP818_DCDC3_CTRL 0x22 |
| 48 | #define AXP818_DCDC4_CTRL 0x23 |
| 49 | #define AXP818_DCDC5_CTRL 0x24 |
| 50 | #define AXP818_DCDC6_CTRL 0x25 |
| 51 | #define AXP818_DCDC7_CTRL 0x26 |
| 52 | |
| 53 | #define AXP818_ALDO1_CTRL 0x28 |
| 54 | #define AXP818_ALDO2_CTRL 0x29 |
| 55 | #define AXP818_ALDO3_CTRL 0x2a |
| 56 | |
| Chen-Yu Tsai | 45f192c | 2016-05-02 10:28:14 +0800 | [diff] [blame] | 57 | #define AXP818_SHUTDOWN 0x32 |
| 58 | #define AXP818_SHUTDOWN_POWEROFF (1 << 7) |
| 59 | |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 60 | /* For axp_gpio.c */ |
| Samuel Holland | 41c1ed4 | 2021-08-22 18:18:04 -0500 | [diff] [blame] | 61 | #ifdef CONFIG_AXP818_POWER |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 62 | #define AXP_POWER_STATUS 0x00 |
| Andre Przywara | 910bea4 | 2022-01-21 13:37:31 +0000 | [diff] [blame] | 63 | #define AXP_POWER_STATUS_ALDO_IN BIT(0) |
| Chen-Yu Tsai | 96234f7 | 2016-03-30 00:26:57 +0800 | [diff] [blame] | 64 | #define AXP_VBUS_IPSOUT 0x30 |
| 65 | #define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) |
| 66 | #define AXP_MISC_CTRL 0x8f |
| 67 | #define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) |
| vishnupatekar | 91bce9c | 2015-11-29 01:07:21 +0800 | [diff] [blame] | 68 | #define AXP_GPIO0_CTRL 0x90 |
| 69 | #define AXP_GPIO1_CTRL 0x92 |
| 70 | #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ |
| 71 | #define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ |
| 72 | #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ |
| 73 | #define AXP_GPIO_STATE 0x94 |
| 74 | #define AXP_GPIO_STATE_OFFSET 0 |
| Samuel Holland | 41c1ed4 | 2021-08-22 18:18:04 -0500 | [diff] [blame] | 75 | #endif |