Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * A driver for the I2C members of the Abracon AB x8xx RTC family, |
| 4 | * and compatible: AB 1805 and AB 0805 |
| 5 | * |
| 6 | * Copyright 2014-2015 Macq S.A. |
| 7 | * Copyright 2020 Linaro |
| 8 | * |
| 9 | * Author: Philippe De Muyter <phdm@macqel.be> |
| 10 | * Author: Alexandre Belloni <alexandre.belloni@bootlin.com> |
| 11 | * Author: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> |
| 12 | * |
| 13 | */ |
| 14 | |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 15 | #include <dm.h> |
| 16 | #include <i2c.h> |
| 17 | #include <rtc.h> |
| 18 | #include <log.h> |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 19 | #include <linux/bitfield.h> |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 20 | |
| 21 | #define ABX8XX_REG_HTH 0x00 |
| 22 | #define ABX8XX_REG_SC 0x01 |
| 23 | #define ABX8XX_REG_MN 0x02 |
| 24 | #define ABX8XX_REG_HR 0x03 |
| 25 | #define ABX8XX_REG_DA 0x04 |
| 26 | #define ABX8XX_REG_MO 0x05 |
| 27 | #define ABX8XX_REG_YR 0x06 |
| 28 | #define ABX8XX_REG_WD 0x07 |
| 29 | |
| 30 | #define ABX8XX_REG_AHTH 0x08 |
| 31 | #define ABX8XX_REG_ASC 0x09 |
| 32 | #define ABX8XX_REG_AMN 0x0a |
| 33 | #define ABX8XX_REG_AHR 0x0b |
| 34 | #define ABX8XX_REG_ADA 0x0c |
| 35 | #define ABX8XX_REG_AMO 0x0d |
| 36 | #define ABX8XX_REG_AWD 0x0e |
| 37 | |
| 38 | #define ABX8XX_REG_STATUS 0x0f |
| 39 | #define ABX8XX_STATUS_AF BIT(2) |
| 40 | #define ABX8XX_STATUS_BLF BIT(4) |
| 41 | #define ABX8XX_STATUS_WDT BIT(6) |
| 42 | |
| 43 | #define ABX8XX_REG_CTRL1 0x10 |
| 44 | #define ABX8XX_CTRL_WRITE BIT(0) |
| 45 | #define ABX8XX_CTRL_ARST BIT(2) |
| 46 | #define ABX8XX_CTRL_12_24 BIT(6) |
| 47 | |
| 48 | #define ABX8XX_REG_CTRL2 0x11 |
| 49 | #define ABX8XX_CTRL2_RSVD BIT(5) |
| 50 | |
| 51 | #define ABX8XX_REG_IRQ 0x12 |
| 52 | #define ABX8XX_IRQ_AIE BIT(2) |
| 53 | #define ABX8XX_IRQ_IM_1_4 (0x3 << 5) |
| 54 | |
| 55 | #define ABX8XX_REG_CD_TIMER_CTL 0x18 |
| 56 | |
| 57 | #define ABX8XX_REG_OSC 0x1c |
| 58 | #define ABX8XX_OSC_FOS BIT(3) |
| 59 | #define ABX8XX_OSC_BOS BIT(4) |
| 60 | #define ABX8XX_OSC_ACAL_512 BIT(5) |
| 61 | #define ABX8XX_OSC_ACAL_1024 BIT(6) |
| 62 | |
| 63 | #define ABX8XX_OSC_OSEL BIT(7) |
| 64 | |
| 65 | #define ABX8XX_REG_OSS 0x1d |
| 66 | #define ABX8XX_OSS_OF BIT(1) |
| 67 | #define ABX8XX_OSS_OMODE BIT(4) |
| 68 | |
| 69 | #define ABX8XX_REG_WDT 0x1b |
| 70 | #define ABX8XX_WDT_WDS BIT(7) |
| 71 | #define ABX8XX_WDT_BMB_MASK 0x7c |
| 72 | #define ABX8XX_WDT_BMB_SHIFT 2 |
| 73 | #define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT) |
| 74 | #define ABX8XX_WDT_WRB_MASK 0x03 |
| 75 | #define ABX8XX_WDT_WRB_1HZ 0x02 |
| 76 | |
| 77 | #define ABX8XX_REG_CFG_KEY 0x1f |
| 78 | #define ABX8XX_CFG_KEY_OSC 0xa1 |
| 79 | #define ABX8XX_CFG_KEY_MISC 0x9d |
| 80 | |
| 81 | #define ABX8XX_REG_ID0 0x28 |
| 82 | |
| 83 | #define ABX8XX_REG_OUT_CTRL 0x30 |
| 84 | #define ABX8XX_OUT_CTRL_EXDS BIT(4) |
| 85 | |
| 86 | #define ABX8XX_REG_TRICKLE 0x20 |
| 87 | #define ABX8XX_TRICKLE_CHARGE_ENABLE 0xa0 |
| 88 | #define ABX8XX_TRICKLE_STANDARD_DIODE 0x8 |
| 89 | #define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4 |
| 90 | |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 91 | #define ABX8XX_REG_EXTRAM 0x3f |
| 92 | #define ABX8XX_EXTRAM_XADS GENMASK(1, 0) |
| 93 | |
| 94 | #define ABX8XX_SRAM_BASE 0x40 |
| 95 | #define ABX8XX_SRAM_WIN_SIZE 0x40U |
| 96 | #define ABX8XX_RAM_SIZE 256 |
| 97 | |
| 98 | #define RAM_ADDR_LOWER GENMASK(5, 0) |
| 99 | #define RAM_ADDR_UPPER GENMASK(7, 6) |
| 100 | |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 101 | static u8 trickle_resistors[] = {0, 3, 6, 11}; |
| 102 | |
| 103 | enum abx80x_chip {AB0801, AB0803, AB0804, AB0805, |
| 104 | AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X}; |
| 105 | |
| 106 | struct abx80x_cap { |
| 107 | u16 pn; |
| 108 | bool has_tc; |
| 109 | bool has_wdog; |
| 110 | }; |
| 111 | |
| 112 | static struct abx80x_cap abx80x_caps[] = { |
| 113 | [AB0801] = {.pn = 0x0801}, |
| 114 | [AB0803] = {.pn = 0x0803}, |
| 115 | [AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true}, |
| 116 | [AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true}, |
| 117 | [AB1801] = {.pn = 0x1801}, |
| 118 | [AB1803] = {.pn = 0x1803}, |
| 119 | [AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true}, |
| 120 | [AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true}, |
| 121 | [RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true}, |
| 122 | [ABX80X] = {.pn = 0} |
| 123 | }; |
| 124 | |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 125 | static int abx80x_rtc_xfer(struct udevice *dev, unsigned int offset, |
| 126 | u8 *val, unsigned int bytes, bool write) |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 127 | { |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 128 | int ret; |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 129 | |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 130 | if (offset + bytes > ABX8XX_RAM_SIZE) |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 131 | return -EINVAL; |
| 132 | |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 133 | while (bytes) { |
| 134 | u8 extram, reg, len, lower, upper; |
| 135 | |
| 136 | lower = FIELD_GET(RAM_ADDR_LOWER, offset); |
| 137 | upper = FIELD_GET(RAM_ADDR_UPPER, offset); |
| 138 | extram = FIELD_PREP(ABX8XX_EXTRAM_XADS, upper); |
| 139 | reg = ABX8XX_SRAM_BASE + lower; |
| 140 | len = min(lower + bytes, ABX8XX_SRAM_WIN_SIZE) - lower; |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 141 | |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 142 | ret = dm_i2c_reg_write(dev, ABX8XX_REG_EXTRAM, extram); |
| 143 | if (ret) |
| 144 | return ret; |
| 145 | |
| 146 | if (write) |
| 147 | ret = dm_i2c_write(dev, reg, val, len); |
| 148 | else |
| 149 | ret = dm_i2c_read(dev, reg, val, len); |
| 150 | if (ret) |
| 151 | return ret; |
| 152 | |
| 153 | offset += len; |
| 154 | val += len; |
| 155 | bytes -= len; |
| 156 | } |
| 157 | |
| 158 | return 0; |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 159 | } |
| 160 | |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 161 | static int abx80x_rtc_read(struct udevice *dev, unsigned int offset, u8 *val, |
| 162 | unsigned int bytes) |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 163 | { |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 164 | return abx80x_rtc_xfer(dev, offset, val, bytes, false); |
| 165 | } |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 166 | |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 167 | static int abx80x_rtc_write(struct udevice *dev, unsigned int offset, |
| 168 | const u8 *val, unsigned int bytes) |
| 169 | { |
| 170 | return abx80x_rtc_xfer(dev, offset, (u8 *)val, bytes, true); |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | static int abx80x_is_rc_mode(struct udevice *dev) |
| 174 | { |
| 175 | int flags = 0; |
| 176 | |
| 177 | flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS); |
| 178 | if (flags < 0) { |
| 179 | log_err("Failed to read autocalibration attribute\n"); |
| 180 | return flags; |
| 181 | } |
| 182 | |
| 183 | return (flags & ABX8XX_OSS_OMODE) ? 1 : 0; |
| 184 | } |
| 185 | |
| 186 | static int abx80x_enable_trickle_charger(struct udevice *dev, u8 trickle_cfg) |
| 187 | { |
| 188 | int err; |
| 189 | |
| 190 | /* |
| 191 | * Write the configuration key register to enable access to the Trickle |
| 192 | * register |
| 193 | */ |
| 194 | err = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY, ABX8XX_CFG_KEY_MISC); |
| 195 | if (err < 0) { |
| 196 | log_err("Unable to write configuration key\n"); |
| 197 | return -EIO; |
| 198 | } |
| 199 | |
| 200 | err = dm_i2c_reg_write(dev, ABX8XX_REG_TRICKLE, |
| 201 | ABX8XX_TRICKLE_CHARGE_ENABLE | trickle_cfg); |
| 202 | if (err < 0) { |
| 203 | log_err("Unable to write trickle register\n"); |
| 204 | return -EIO; |
| 205 | } |
| 206 | |
| 207 | return 0; |
| 208 | } |
| 209 | |
| 210 | static int abx80x_rtc_read_time(struct udevice *dev, struct rtc_time *tm) |
| 211 | { |
| 212 | unsigned char buf[8]; |
| 213 | int err, flags, rc_mode = 0; |
| 214 | |
| 215 | /* Read the Oscillator Failure only in XT mode */ |
| 216 | rc_mode = abx80x_is_rc_mode(dev); |
| 217 | if (rc_mode < 0) |
| 218 | return rc_mode; |
| 219 | |
| 220 | if (!rc_mode) { |
| 221 | flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS); |
| 222 | if (flags < 0) { |
| 223 | log_err("Unable to read oscillator status.\n"); |
| 224 | return flags; |
| 225 | } |
| 226 | |
| 227 | if (flags & ABX8XX_OSS_OF) |
| 228 | log_debug("Oscillator fail, data is not accurate.\n"); |
| 229 | } |
| 230 | |
| 231 | err = dm_i2c_read(dev, ABX8XX_REG_HTH, |
| 232 | buf, sizeof(buf)); |
| 233 | if (err < 0) { |
| 234 | log_err("Unable to read date\n"); |
| 235 | return -EIO; |
| 236 | } |
| 237 | |
| 238 | tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F); |
| 239 | tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F); |
| 240 | tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F); |
| 241 | tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7; |
| 242 | tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F); |
| 243 | tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F); |
| 244 | tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 2000; |
| 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | static int abx80x_rtc_set_time(struct udevice *dev, const struct rtc_time *tm) |
| 250 | { |
| 251 | unsigned char buf[8]; |
| 252 | int err, flags; |
| 253 | |
| 254 | if (tm->tm_year < 2000) |
| 255 | return -EINVAL; |
| 256 | |
| 257 | buf[ABX8XX_REG_HTH] = 0; |
| 258 | buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec); |
| 259 | buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min); |
| 260 | buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour); |
| 261 | buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday); |
| 262 | buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon); |
| 263 | buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 2000); |
| 264 | buf[ABX8XX_REG_WD] = tm->tm_wday; |
| 265 | |
| 266 | err = dm_i2c_write(dev, ABX8XX_REG_HTH, |
| 267 | buf, sizeof(buf)); |
| 268 | if (err < 0) { |
| 269 | log_err("Unable to write to date registers\n"); |
| 270 | return -EIO; |
| 271 | } |
| 272 | |
| 273 | /* Clear the OF bit of Oscillator Status Register */ |
| 274 | flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS); |
| 275 | if (flags < 0) { |
| 276 | log_err("Unable to read oscillator status.\n"); |
| 277 | return flags; |
| 278 | } |
| 279 | |
| 280 | err = dm_i2c_reg_write(dev, ABX8XX_REG_OSS, |
| 281 | flags & ~ABX8XX_OSS_OF); |
| 282 | if (err < 0) { |
| 283 | log_err("Unable to write oscillator status register\n"); |
| 284 | return err; |
| 285 | } |
| 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
| 290 | static int abx80x_rtc_set_autocalibration(struct udevice *dev, |
| 291 | int autocalibration) |
| 292 | { |
| 293 | int retval, flags = 0; |
| 294 | |
| 295 | if (autocalibration != 0 && autocalibration != 1024 && |
| 296 | autocalibration != 512) { |
| 297 | log_err("autocalibration value outside permitted range\n"); |
| 298 | return -EINVAL; |
| 299 | } |
| 300 | |
| 301 | flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSC); |
| 302 | if (flags < 0) |
| 303 | return flags; |
| 304 | |
| 305 | if (autocalibration == 0) { |
| 306 | flags &= ~(ABX8XX_OSC_ACAL_512 | ABX8XX_OSC_ACAL_1024); |
| 307 | } else if (autocalibration == 1024) { |
| 308 | /* 1024 autocalibration is 0x10 */ |
| 309 | flags |= ABX8XX_OSC_ACAL_1024; |
| 310 | flags &= ~(ABX8XX_OSC_ACAL_512); |
| 311 | } else { |
| 312 | /* 512 autocalibration is 0x11 */ |
| 313 | flags |= (ABX8XX_OSC_ACAL_1024 | ABX8XX_OSC_ACAL_512); |
| 314 | } |
| 315 | |
| 316 | /* Unlock write access to Oscillator Control Register */ |
| 317 | retval = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY, |
| 318 | ABX8XX_CFG_KEY_OSC); |
| 319 | if (retval < 0) { |
| 320 | log_err("Failed to write CONFIG_KEY register\n"); |
| 321 | return retval; |
| 322 | } |
| 323 | |
| 324 | retval = dm_i2c_reg_write(dev, ABX8XX_REG_OSC, flags); |
| 325 | |
| 326 | return retval; |
| 327 | } |
| 328 | |
| 329 | static int abx80x_rtc_get_autocalibration(struct udevice *dev) |
| 330 | { |
| 331 | int flags = 0, autocalibration; |
| 332 | |
| 333 | flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSC); |
| 334 | if (flags < 0) |
| 335 | return flags; |
| 336 | |
| 337 | if (flags & ABX8XX_OSC_ACAL_512) |
| 338 | autocalibration = 512; |
| 339 | else if (flags & ABX8XX_OSC_ACAL_1024) |
| 340 | autocalibration = 1024; |
| 341 | else |
| 342 | autocalibration = 0; |
| 343 | |
| 344 | return autocalibration; |
| 345 | } |
| 346 | |
| 347 | static struct rtc_time default_tm = { 0, 0, 0, 1, 1, 2000, 6, 0, 0 }; |
| 348 | |
| 349 | static int abx80x_rtc_reset(struct udevice *dev) |
| 350 | { |
| 351 | int ret = 0; |
| 352 | |
| 353 | int autocalib = abx80x_rtc_get_autocalibration(dev); |
| 354 | |
| 355 | if (autocalib != 0) |
| 356 | abx80x_rtc_set_autocalibration(dev, 0); |
| 357 | |
| 358 | ret = abx80x_rtc_set_time(dev, &default_tm); |
| 359 | if (ret != 0) { |
| 360 | log_err("cannot set time to default_tm. error %d\n", ret); |
| 361 | return ret; |
| 362 | } |
| 363 | |
| 364 | return ret; |
| 365 | } |
| 366 | |
| 367 | static const struct rtc_ops abx80x_rtc_ops = { |
| 368 | .get = abx80x_rtc_read_time, |
| 369 | .set = abx80x_rtc_set_time, |
Sean Anderson | 4d68321 | 2022-12-02 10:35:19 -0500 | [diff] [blame] | 370 | .reset = abx80x_rtc_reset, |
| 371 | .read = abx80x_rtc_read, |
| 372 | .write = abx80x_rtc_write, |
Ying-Chun Liu (PaulLiu) | f9b8730 | 2021-01-15 13:53:02 +0800 | [diff] [blame] | 373 | }; |
| 374 | |
| 375 | static int abx80x_dt_trickle_cfg(struct udevice *dev) |
| 376 | { |
| 377 | const char *diode; |
| 378 | int trickle_cfg = 0; |
| 379 | int i, ret = 0; |
| 380 | u32 tmp; |
| 381 | |
| 382 | diode = ofnode_read_string(dev_ofnode(dev), "abracon,tc-diode"); |
| 383 | if (!diode) |
| 384 | return ret; |
| 385 | |
| 386 | if (!strcmp(diode, "standard")) { |
| 387 | trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE; |
| 388 | } else if (!strcmp(diode, "schottky")) { |
| 389 | trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE; |
| 390 | } else { |
| 391 | log_err("Invalid tc-diode value: %s\n", diode); |
| 392 | return -EINVAL; |
| 393 | } |
| 394 | |
| 395 | ret = ofnode_read_u32(dev_ofnode(dev), "abracon,tc-resistor", &tmp); |
| 396 | if (ret) |
| 397 | return ret; |
| 398 | |
| 399 | for (i = 0; i < sizeof(trickle_resistors); i++) |
| 400 | if (trickle_resistors[i] == tmp) |
| 401 | break; |
| 402 | |
| 403 | if (i == sizeof(trickle_resistors)) { |
| 404 | log_err("Invalid tc-resistor value: %u\n", tmp); |
| 405 | return -EINVAL; |
| 406 | } |
| 407 | |
| 408 | return (trickle_cfg | i); |
| 409 | } |
| 410 | |
| 411 | static int abx80x_probe(struct udevice *dev) |
| 412 | { |
| 413 | int i, data, err, trickle_cfg = -EINVAL; |
| 414 | unsigned char buf[7]; |
| 415 | unsigned int part = dev->driver_data; |
| 416 | unsigned int partnumber; |
| 417 | unsigned int majrev, minrev; |
| 418 | unsigned int lot; |
| 419 | unsigned int wafer; |
| 420 | unsigned int uid; |
| 421 | |
| 422 | err = dm_i2c_read(dev, ABX8XX_REG_ID0, buf, sizeof(buf)); |
| 423 | if (err < 0) { |
| 424 | log_err("Unable to read partnumber\n"); |
| 425 | return -EIO; |
| 426 | } |
| 427 | |
| 428 | partnumber = (buf[0] << 8) | buf[1]; |
| 429 | majrev = buf[2] >> 3; |
| 430 | minrev = buf[2] & 0x7; |
| 431 | lot = ((buf[4] & 0x80) << 2) | ((buf[6] & 0x80) << 1) | buf[3]; |
| 432 | uid = ((buf[4] & 0x7f) << 8) | buf[5]; |
| 433 | wafer = (buf[6] & 0x7c) >> 2; |
| 434 | log_debug("model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n", |
| 435 | partnumber, majrev, minrev, lot, wafer, uid); |
| 436 | |
| 437 | data = dm_i2c_reg_read(dev, ABX8XX_REG_CTRL1); |
| 438 | if (data < 0) { |
| 439 | log_err("Unable to read control register\n"); |
| 440 | return -EIO; |
| 441 | } |
| 442 | |
| 443 | err = dm_i2c_reg_write(dev, ABX8XX_REG_CTRL1, |
| 444 | ((data & ~(ABX8XX_CTRL_12_24 | |
| 445 | ABX8XX_CTRL_ARST)) | |
| 446 | ABX8XX_CTRL_WRITE)); |
| 447 | if (err < 0) { |
| 448 | log_err("Unable to write control register\n"); |
| 449 | return -EIO; |
| 450 | } |
| 451 | |
| 452 | /* Configure RV1805 specifics */ |
| 453 | if (part == RV1805) { |
| 454 | /* |
| 455 | * Avoid accidentally entering test mode. This can happen |
| 456 | * on the RV1805 in case the reserved bit 5 in control2 |
| 457 | * register is set. RV-1805-C3 datasheet indicates that |
| 458 | * the bit should be cleared in section 11h - Control2. |
| 459 | */ |
| 460 | data = dm_i2c_reg_read(dev, ABX8XX_REG_CTRL2); |
| 461 | if (data < 0) { |
| 462 | log_err("Unable to read control2 register\n"); |
| 463 | return -EIO; |
| 464 | } |
| 465 | |
| 466 | err = dm_i2c_reg_write(dev, ABX8XX_REG_CTRL2, |
| 467 | data & ~ABX8XX_CTRL2_RSVD); |
| 468 | if (err < 0) { |
| 469 | log_err("Unable to write control2 register\n"); |
| 470 | return -EIO; |
| 471 | } |
| 472 | |
| 473 | /* |
| 474 | * Avoid extra power leakage. The RV1805 uses smaller |
| 475 | * 10pin package and the EXTI input is not present. |
| 476 | * Disable it to avoid leakage. |
| 477 | */ |
| 478 | data = dm_i2c_reg_read(dev, ABX8XX_REG_OUT_CTRL); |
| 479 | if (data < 0) { |
| 480 | log_err("Unable to read output control register\n"); |
| 481 | return -EIO; |
| 482 | } |
| 483 | |
| 484 | /* |
| 485 | * Write the configuration key register to enable access to |
| 486 | * the config2 register |
| 487 | */ |
| 488 | err = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY, |
| 489 | ABX8XX_CFG_KEY_MISC); |
| 490 | if (err < 0) { |
| 491 | log_err("Unable to write configuration key\n"); |
| 492 | return -EIO; |
| 493 | } |
| 494 | |
| 495 | err = dm_i2c_reg_write(dev, ABX8XX_REG_OUT_CTRL, |
| 496 | data | ABX8XX_OUT_CTRL_EXDS); |
| 497 | if (err < 0) { |
| 498 | log_err("Unable to write output control register\n"); |
| 499 | return -EIO; |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | /* part autodetection */ |
| 504 | if (part == ABX80X) { |
| 505 | for (i = 0; abx80x_caps[i].pn; i++) |
| 506 | if (partnumber == abx80x_caps[i].pn) |
| 507 | break; |
| 508 | if (abx80x_caps[i].pn == 0) { |
| 509 | log_err("Unknown part: %04x\n", partnumber); |
| 510 | return -EINVAL; |
| 511 | } |
| 512 | part = i; |
| 513 | } |
| 514 | |
| 515 | if (partnumber != abx80x_caps[part].pn) { |
| 516 | log_err("partnumber mismatch %04x != %04x\n", |
| 517 | partnumber, abx80x_caps[part].pn); |
| 518 | return -EINVAL; |
| 519 | } |
| 520 | |
| 521 | if (abx80x_caps[part].has_tc) |
| 522 | trickle_cfg = abx80x_dt_trickle_cfg(dev); |
| 523 | |
| 524 | if (trickle_cfg > 0) { |
| 525 | log_debug("Enabling trickle charger: %02x\n", trickle_cfg); |
| 526 | abx80x_enable_trickle_charger(dev, trickle_cfg); |
| 527 | } |
| 528 | |
| 529 | err = dm_i2c_reg_write(dev, ABX8XX_REG_CD_TIMER_CTL, BIT(2)); |
| 530 | if (err) |
| 531 | return err; |
| 532 | |
| 533 | return 0; |
| 534 | } |
| 535 | |
| 536 | static const struct udevice_id abx80x_of_match[] = { |
| 537 | { |
| 538 | .compatible = "abracon,abx80x", |
| 539 | .data = ABX80X |
| 540 | }, |
| 541 | { |
| 542 | .compatible = "abracon,ab0801", |
| 543 | .data = AB0801 |
| 544 | }, |
| 545 | { |
| 546 | .compatible = "abracon,ab0803", |
| 547 | .data = AB0803 |
| 548 | }, |
| 549 | { |
| 550 | .compatible = "abracon,ab0804", |
| 551 | .data = AB0804 |
| 552 | }, |
| 553 | { |
| 554 | .compatible = "abracon,ab0805", |
| 555 | .data = AB0805 |
| 556 | }, |
| 557 | { |
| 558 | .compatible = "abracon,ab1801", |
| 559 | .data = AB1801 |
| 560 | }, |
| 561 | { |
| 562 | .compatible = "abracon,ab1803", |
| 563 | .data = AB1803 |
| 564 | }, |
| 565 | { |
| 566 | .compatible = "abracon,ab1804", |
| 567 | .data = AB1804 |
| 568 | }, |
| 569 | { |
| 570 | .compatible = "abracon,ab1805", |
| 571 | .data = AB1805 |
| 572 | }, |
| 573 | { |
| 574 | .compatible = "microcrystal,rv1805", |
| 575 | .data = RV1805 |
| 576 | }, |
| 577 | { } |
| 578 | }; |
| 579 | |
| 580 | U_BOOT_DRIVER(abx80x_rtc) = { |
| 581 | .name = "rtc-abx80x", |
| 582 | .id = UCLASS_RTC, |
| 583 | .probe = abx80x_probe, |
| 584 | .of_match = abx80x_of_match, |
| 585 | .ops = &abx80x_rtc_ops, |
| 586 | }; |