blob: c24f8cf1eb1faf94f89bfcfc53d6eec9ba3a66c1 [file] [log] [blame]
Mark Kettenisf8463d62022-01-22 20:38:11 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017 NXP Semiconductors
4 * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com>
5 */
6
Mark Kettenisf8463d62022-01-22 20:38:11 +01007#include <dm.h>
Simon Glass4e969d62023-05-04 16:55:07 -06008#include <init.h>
Mark Kettenisf8463d62022-01-22 20:38:11 +01009#include <pci.h>
10#include "nvme.h"
11
12static int nvme_bind(struct udevice *udev)
13{
14 static int ndev_num;
15 char name[20];
16
17 sprintf(name, "nvme#%d", ndev_num++);
18
19 return device_set_name(udev, name);
20}
21
22static int nvme_probe(struct udevice *udev)
23{
24 struct nvme_dev *ndev = dev_get_priv(udev);
25 struct pci_child_plat *pplat;
26
27 pplat = dev_get_parent_plat(udev);
28 sprintf(ndev->vendor, "0x%.4x", pplat->vendor);
29
30 ndev->instance = trailing_strtol(udev->name);
Andrew Scull58c61022022-04-21 16:11:10 +000031 ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0,
Andrew Scull6520c822022-04-21 16:11:13 +000032 PCI_REGION_TYPE, PCI_REGION_MEM);
Simon Glass4e969d62023-05-04 16:55:07 -060033
34 /* Turn on bus-mastering */
35 dm_pci_clrset_config16(udev, PCI_COMMAND, 0, PCI_COMMAND_MASTER);
36
Mark Kettenisf8463d62022-01-22 20:38:11 +010037 return nvme_init(udev);
38}
39
40U_BOOT_DRIVER(nvme) = {
41 .name = "nvme",
42 .id = UCLASS_NVME,
43 .bind = nvme_bind,
44 .probe = nvme_probe,
45 .priv_auto = sizeof(struct nvme_dev),
46};
47
48struct pci_device_id nvme_supported[] = {
49 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) },
50 {}
51};
52
53U_BOOT_PCI_DEVICE(nvme, nvme_supported);