blob: 46cc3c03fffb486f2779b0809816f69d49f64703 [file] [log] [blame]
Andy Yanb352c842023-08-05 20:00:11 +08001CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT=y
3CONFIG_COUNTER_FREQUENCY=24000000
4CONFIG_ARCH_ROCKCHIP=y
Jonas Karlman737739e2024-05-04 19:43:00 +00005CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-lubancat-2"
Andy Yanb352c842023-08-05 20:00:11 +08006CONFIG_ROCKCHIP_RK3568=y
Andy Yanb352c842023-08-05 20:00:11 +08007CONFIG_SPL_SERIAL=y
Tom Rinic427a582024-10-08 09:18:32 -06008CONFIG_SYS_LOAD_ADDR=0xc00800
Andy Yanb352c842023-08-05 20:00:11 +08009CONFIG_DEBUG_UART_BASE=0xFE660000
10CONFIG_DEBUG_UART_CLOCK=24000000
Andy Yanb352c842023-08-05 20:00:11 +080011CONFIG_DEBUG_UART=y
Tom Rinic427a582024-10-08 09:18:32 -060012CONFIG_EFI_VAR_BUF_SIZE=16384
Andy Yanb352c842023-08-05 20:00:11 +080013CONFIG_FIT=y
14CONFIG_FIT_VERBOSE=y
15CONFIG_SPL_FIT_SIGNATURE=y
16CONFIG_SPL_LOAD_FIT=y
17CONFIG_LEGACY_IMAGE_FORMAT=y
18CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
19# CONFIG_DISPLAY_CPUINFO is not set
20CONFIG_DISPLAY_BOARDINFO_LATE=y
21CONFIG_SPL_MAX_SIZE=0x40000
22CONFIG_SPL_PAD_TO=0x7f8000
Andy Yanb352c842023-08-05 20:00:11 +080023# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Andy Yanb352c842023-08-05 20:00:11 +080024CONFIG_SPL_ATF=y
25CONFIG_CMD_GPIO=y
26CONFIG_CMD_GPT=y
27CONFIG_CMD_I2C=y
28CONFIG_CMD_MMC=y
29CONFIG_CMD_USB=y
30# CONFIG_CMD_SETEXPR is not set
31CONFIG_CMD_PMIC=y
32CONFIG_CMD_REGULATOR=y
33# CONFIG_SPL_DOS_PARTITION is not set
34CONFIG_SPL_OF_CONTROL=y
35CONFIG_OF_LIVE=y
36CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
37CONFIG_SPL_DM_SEQ_ALIAS=y
38CONFIG_SPL_REGMAP=y
39CONFIG_SPL_SYSCON=y
40CONFIG_SPL_CLK=y
41CONFIG_ROCKCHIP_GPIO=y
42CONFIG_SYS_I2C_ROCKCHIP=y
43CONFIG_MISC=y
44CONFIG_SUPPORT_EMMC_RPMB=y
45CONFIG_MMC_DW=y
46CONFIG_MMC_DW_ROCKCHIP=y
47CONFIG_MMC_SDHCI=y
48CONFIG_MMC_SDHCI_SDMA=y
49CONFIG_MMC_SDHCI_ROCKCHIP=y
50# CONFIG_SPI_FLASH is not set
Jonas Karlmand21f0092023-10-01 19:17:21 +000051CONFIG_PHY_REALTEK=y
52CONFIG_DWC_ETH_QOS=y
53CONFIG_DWC_ETH_QOS_ROCKCHIP=y
Andy Yanb352c842023-08-05 20:00:11 +080054CONFIG_PHY_ROCKCHIP_INNO_USB2=y
55CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
56CONFIG_SPL_PINCTRL=y
57CONFIG_DM_PMIC=y
58CONFIG_PMIC_RK8XX=y
59CONFIG_REGULATOR_RK8XX=y
60CONFIG_PWM_ROCKCHIP=y
61CONFIG_SPL_RAM=y
62CONFIG_BAUDRATE=1500000
63CONFIG_DEBUG_UART_SHIFT=2
64CONFIG_SYS_NS16550_MEM32=y
65CONFIG_SYSRESET=y
66CONFIG_USB=y
67CONFIG_USB_XHCI_HCD=y
68CONFIG_USB_EHCI_HCD=y
69CONFIG_USB_EHCI_GENERIC=y
70CONFIG_USB_OHCI_HCD=y
71CONFIG_USB_OHCI_GENERIC=y
72CONFIG_USB_DWC3=y
73CONFIG_USB_DWC3_GENERIC=y
74CONFIG_ERRNO_STR=y