blob: 96d2a3fc6c73fe0d78ac9878a4a192492e3de1b7 [file] [log] [blame]
Patrick Wildt53d0f0a2023-02-06 00:48:26 +01001/*
2 * Copyright 2019 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Generated code from MX8M_DDR_tool
7 * Align with uboot version:
8 * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
9 */
10#include "lpddr4_timing_ch2.h"
11
12static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
13 /** Initialize DDRC registers **/
14 { DDRC_DBG1(0), 1 },
15 /* selfref_en=1, SDRAM enter self-refresh state */
16 { DDRC_PWRCTL(0), 1 },
17 { DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
18 { DDRC_MSTR2(0), 0 },
19 { DDRC_DERATEEN(0), 0x0203 },
20 { DDRC_DERATEINT(0), 0x0003e800 },
21 { DDRC_RFSHTMG(0), 0x006100e0 },
22 { DDRC_INIT0(0), 0xc003061c },
23 { DDRC_INIT1(0), 0x009e0000 },
24 { DDRC_INIT3(0), 0x00d4002d },
25 { DDRC_INIT4(0), CH2_VAL_INIT4 },
26 { DDRC_INIT6(0), 0x0066004a },
27 { DDRC_INIT7(0), 0x0016004a },
28 { DDRC_DRAMTMG0(0), 0x1a201b22 },
29 { DDRC_DRAMTMG1(0), 0x00060633 },
30 { DDRC_DRAMTMG3(0), 0x00c0c000 },
31 { DDRC_DRAMTMG4(0), 0x0f04080f },
32 { DDRC_DRAMTMG5(0), 0x02040c0c },
33 { DDRC_DRAMTMG6(0), 0x01010007 },
34 { DDRC_DRAMTMG7(0), 0x0401 },
35 { DDRC_DRAMTMG12(0), 0x00020600 },
36 { DDRC_DRAMTMG13(0), 0x0c100002 },
37 { DDRC_DRAMTMG14(0), 0xe6 },
38 { DDRC_DRAMTMG17(0), 0x00a00050 },
39 { DDRC_ZQCTL0(0), 0xc3200018 },
40 { DDRC_ZQCTL1(0), 0x028061a8 },
41 { DDRC_ZQCTL2(0), 0 },
42 { DDRC_DFITMG0(0), 0x0497820a },
43 { DDRC_DFITMG1(0), 0x00080303 },
44 { DDRC_DFIUPD0(0), 0xe0400018 },
45 { DDRC_DFIUPD1(0), 0x00df00e4 },
46 { DDRC_DFIUPD2(0), 0x80000000 },
47 { DDRC_DFIMISC(0), 0x11 },
48 { DDRC_DFITMG2(0), 0x170a },
49 { DDRC_DBICTL(0), 1 },
50 { DDRC_DFIPHYMSTR(0), 1 },
51 { DDRC_RANKCTL(0), 0x0639 },
52 { DDRC_DRAMTMG2(0), 0x070e1617 },
53
54 /* address mapping */
55 { DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
56 { DDRC_ADDRMAP3(0), 0 },
57 /* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
58 { DDRC_ADDRMAP4(0), 0x1f1f },
59 /* bank interleave */
60 /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
61 { DDRC_ADDRMAP1(0), 0x00080808 },
62 /* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
63 { DDRC_ADDRMAP5(0), 0x07070707 },
64 /* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
65 { DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
66 { DDRC_ADDRMAP7(0), 0x0f0f },
67 { DDRC_FREQ1_DERATEEN(0), 1 },
68 { DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
69 { DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
70 { DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
71 { DDRC_FREQ1_INIT3(0), 0x00940009 },
72 { DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
73 { DDRC_FREQ1_INIT6(0), 0x0066004a },
74 { DDRC_FREQ1_INIT7(0), 0x0016004a },
75 { DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
76 { DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
77 { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
78 { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
79 { DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
80 { DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
81 { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
82 { DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
83 { DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
84 { DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
85 { DDRC_FREQ1_DRAMTMG14(0), 0x31 },
86 { DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
87 { DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
88 { DDRC_FREQ1_DFITMG0(0), 0x03858202 },
89 { DDRC_FREQ1_DFITMG1(0), 0x00080303 },
90 { DDRC_FREQ1_DFITMG2(0), 0x0502 },
91 { DDRC_ODTMAP(0), 0 },
92 { DDRC_SCHED(0), 0x29001505 },
93 { DDRC_SCHED1(0), 0x2c },
94 { DDRC_PERFHPR1(0), 0x5900575b },
95 { DDRC_PERFLPR1(0), 0x90000096 },
96 { DDRC_PERFWR1(0), 0x1000012c },
97 { DDRC_DBG0(0), 0x16 },
98 { DDRC_DBG1(0), 0 },
99 { DDRC_DBGCMD(0), 0 },
100 { DDRC_SWCTL(0), 1 },
101 { DDRC_POISONCFG(0), 0x11 },
102 { DDRC_PCCFG(0), 0x0111 },
103 { DDRC_PCFGR_0(0), 0x10f3 },
104 { DDRC_PCFGW_0(0), 0x72ff },
105 { DDRC_PCTRL_0(0), 1 },
106 { DDRC_PCFGQOS0_0(0), 0x0e00 },
107 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
108 { DDRC_PCFGWQOS0_0(0), 0x0e00 },
109 { DDRC_PCFGWQOS1_0(0), 0xffff },
110};
111
112/* PHY Initialize Configuration */
113static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
114 { 0x100a0, 0 },
115 { 0x100a1, 1 },
116 { 0x100a2, 2 },
117 { 0x100a3, 3 },
118 { 0x100a4, 4 },
119 { 0x100a5, 5 },
120 { 0x100a6, 6 },
121 { 0x100a7, 7 },
122 { 0x110a0, 0 },
123 { 0x110a1, 1 },
124 { 0x110a2, 2 },
125 { 0x110a3, 3 },
126 { 0x110a4, 4 },
127 { 0x110a5, 5 },
128 { 0x110a6, 6 },
129 { 0x110a7, 7 },
130 { 0x120a0, 0 },
131 { 0x120a1, 1 },
132 { 0x120a2, 2 },
133 { 0x120a3, 3 },
134 { 0x120a4, 4 },
135 { 0x120a5, 5 },
136 { 0x120a6, 6 },
137 { 0x120a7, 7 },
138 { 0x130a0, 0 },
139 { 0x130a1, 1 },
140 { 0x130a2, 2 },
141 { 0x130a3, 3 },
142 { 0x130a4, 4 },
143 { 0x130a5, 5 },
144 { 0x130a6, 6 },
145 { 0x130a7, 7 },
146 { 0x1005f, 0x01ff },
147 { 0x1015f, 0x01ff },
148 { 0x1105f, 0x01ff },
149 { 0x1115f, 0x01ff },
150 { 0x1205f, 0x01ff },
151 { 0x1215f, 0x01ff },
152 { 0x1305f, 0x01ff },
153 { 0x1315f, 0x01ff },
154 { 0x11005f, 0x01ff },
155 { 0x11015f, 0x01ff },
156 { 0x11105f, 0x01ff },
157 { 0x11115f, 0x01ff },
158 { 0x11205f, 0x01ff },
159 { 0x11215f, 0x01ff },
160 { 0x11305f, 0x01ff },
161 { 0x11315f, 0x01ff },
162 { 0x0055, 0x01ff },
163 { 0x1055, 0x01ff },
164 { 0x2055, 0x01ff },
165 { 0x3055, 0x01ff },
166 { 0x4055, 0x01ff },
167 { 0x5055, 0x01ff },
168 { 0x6055, 0x01ff },
169 { 0x7055, 0x01ff },
170 { 0x8055, 0x01ff },
171 { 0x9055, 0x01ff },
172 { 0x200c5, 0x19 },
173 { 0x1200c5, 7 },
174 { 0x2002e, 2 },
175 { 0x12002e, 1 },
176 { 0x90204, 0 },
177 { 0x190204, 0 },
178 { 0x20024, 0x01ab },
179 { 0x2003a, 0 },
180 { 0x120024, 0x01ab },
181 { 0x2003a, 0 },
182 { 0x20056, 3 },
183 { 0x120056, 3 },
184 { 0x1004d, 0x0e00 },
185 { 0x1014d, 0x0e00 },
186 { 0x1104d, 0x0e00 },
187 { 0x1114d, 0x0e00 },
188 { 0x1204d, 0x0e00 },
189 { 0x1214d, 0x0e00 },
190 { 0x1304d, 0x0e00 },
191 { 0x1314d, 0x0e00 },
192 { 0x11004d, 0x0e00 },
193 { 0x11014d, 0x0e00 },
194 { 0x11104d, 0x0e00 },
195 { 0x11114d, 0x0e00 },
196 { 0x11204d, 0x0e00 },
197 { 0x11214d, 0x0e00 },
198 { 0x11304d, 0x0e00 },
199 { 0x11314d, 0x0e00 },
200 { 0x10049, 0x0eba },
201 { 0x10149, 0x0eba },
202 { 0x11049, 0x0eba },
203 { 0x11149, 0x0eba },
204 { 0x12049, 0x0eba },
205 { 0x12149, 0x0eba },
206 { 0x13049, 0x0eba },
207 { 0x13149, 0x0eba },
208 { 0x110049, 0x0eba },
209 { 0x110149, 0x0eba },
210 { 0x111049, 0x0eba },
211 { 0x111149, 0x0eba },
212 { 0x112049, 0x0eba },
213 { 0x112149, 0x0eba },
214 { 0x113049, 0x0eba },
215 { 0x113149, 0x0eba },
216 { 0x0043, 0x63 },
217 { 0x1043, 0x63 },
218 { 0x2043, 0x63 },
219 { 0x3043, 0x63 },
220 { 0x4043, 0x63 },
221 { 0x5043, 0x63 },
222 { 0x6043, 0x63 },
223 { 0x7043, 0x63 },
224 { 0x8043, 0x63 },
225 { 0x9043, 0x63 },
226 { 0x20018, 3 },
227 { 0x20075, 4 },
228 { 0x20050, 0 },
229 { 0x20008, 0x0320 },
230 { 0x120008, 0xa7 },
231 { 0x20088, 9 },
232 { 0x200b2, 0xdc },
233 { 0x10043, 0x05a1 },
234 { 0x10143, 0x05a1 },
235 { 0x11043, 0x05a1 },
236 { 0x11143, 0x05a1 },
237 { 0x12043, 0x05a1 },
238 { 0x12143, 0x05a1 },
239 { 0x13043, 0x05a1 },
240 { 0x13143, 0x05a1 },
241 { 0x1200b2, 0xdc },
242 { 0x110043, 0x05a1 },
243 { 0x110143, 0x05a1 },
244 { 0x111043, 0x05a1 },
245 { 0x111143, 0x05a1 },
246 { 0x112043, 0x05a1 },
247 { 0x112143, 0x05a1 },
248 { 0x113043, 0x05a1 },
249 { 0x113143, 0x05a1 },
250 { 0x200fa, 1 },
251 { 0x1200fa, 1 },
252 { 0x20019, 1 },
253 { 0x120019, 1 },
254 { 0x200f0, 0 },
255 { 0x200f1, 0 },
256 { 0x200f2, 0x4444 },
257 { 0x200f3, 0x8888 },
258 { 0x200f4, 0x5555 },
259 { 0x200f5, 0 },
260 { 0x200f6, 0 },
261 { 0x200f7, 0xf000 },
262 { 0x20025, 0 },
263 { 0x2002d, 0 },
264 { 0x12002d, 0 },
265 { 0x200c7, 0x80 },
266 { 0x1200c7, 0x80 },
267 { 0x200ca, 0x0106 },
268 { 0x1200ca, 0x0106 },
269 { 0x20110, 2 },
270 { 0x20111, 3 },
271 { 0x20112, 4 },
272 { 0x20113, 5 },
273 { 0x20114, 0 },
274 { 0x20115, 1 },
275};
276
277/* P0 message block parameter for training firmware */
278static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
279 { 0xd0000, 0 },
280 { 0x54003, 0x0c80 },
281 { 0x54004, 2 },
282 { 0x54005, 0x2228 },
283 { 0x54006, LPDDR4_PHY_VREF_VALUE },
284 { 0x54008, 0x131f },
285 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
286 { 0x5400b, 2 },
287 { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
288 { 0x54019, 0x2dd4 },
289 { 0x5401a, 0x31 },
290 { 0x5401b, 0x4a66 },
291 { 0x5401c, 0x4a08 },
292 { 0x5401e, 0x16 },
293 { 0x5401f, 0x2dd4 },
294 { 0x54020, 0x31 },
295 { 0x54021, 0x4a66 },
296 { 0x54022, 0x4a08 },
297 { 0x54024, 0x16 },
298 { 0x5402b, 0x1000 },
299 { 0x5402c, CH2_LPDDR4_CS },
300 { 0x54032, 0xd400 },
301 { 0x54033, 0x312d },
302 { 0x54034, 0x6600 },
303 { 0x54035, 0x084a },
304 { 0x54036, 0x4a },
305 { 0x54037, 0x1600 },
306 { 0x54038, 0xd400 },
307 { 0x54039, 0x312d },
308 { 0x5403a, 0x6600 },
309 { 0x5403b, 0x084a },
310 { 0x5403c, 0x4a },
311 { 0x5403d, 0x1600 },
312 { 0xd0000, 1 },
313};
314
Patrick Wildt53d0f0a2023-02-06 00:48:26 +0100315/* P1 message block parameter for training firmware */
316static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
317 { 0xd0000, 0 },
318 { 0x54002, 1 },
319 { 0x54003, 0x029c },
320 { 0x54004, 2 },
321 { 0x54005, 0x2228 },
322 { 0x54006, LPDDR4_PHY_VREF_VALUE },
323 { 0x54008, 0x121f },
324 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
325 { 0x5400b, 2 },
326 { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
327 { 0x54019, 0x0994 },
328 { 0x5401a, 0x31 },
329 { 0x5401b, 0x4a66 },
330 { 0x5401c, 0x4a08 },
331 { 0x5401e, 0x16 },
332 { 0x5401f, 0x0994 },
333 { 0x54020, 0x31 },
334 { 0x54021, 0x4a66 },
335 { 0x54022, 0x4a08 },
336 { 0x54024, 0x16 },
337 { 0x5402b, 0x1000 },
338 { 0x5402c, CH2_LPDDR4_CS },
339 { 0x54032, 0x9400 },
340 { 0x54033, 0x3109 },
341 { 0x54034, 0x6600 },
342 { 0x54035, 0x084a },
343 { 0x54036, 0x4a },
344 { 0x54037, 0x1600 },
345 { 0x54038, 0x9400 },
346 { 0x54039, 0x3109 },
347 { 0x5403a, 0x6600 },
348 { 0x5403b, 0x084a },
349 { 0x5403c, 0x4a },
350 { 0x5403d, 0x1600 },
351 { 0xd0000, 1 },
352};
353
Patrick Wildt53d0f0a2023-02-06 00:48:26 +0100354/* P0 2D message block parameter for training firmware */
355static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
356 { 0xd0000, 0 },
357 { 0x54003, 0x0c80 },
358 { 0x54004, 2 },
359 { 0x54005, 0x2228 },
360 { 0x54006, LPDDR4_PHY_VREF_VALUE },
361 { 0x54008, 0x61 },
362 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
363 { 0x5400b, 2 },
364 { 0x5400d, 0x0100 },
365 { 0x5400f, 0x0100 },
366 { 0x54010, 0x1f7f },
367 { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
368 { 0x54019, 0x2dd4 },
369 { 0x5401a, 0x31 },
370 { 0x5401b, 0x4a66 },
371 { 0x5401c, 0x4a08 },
372 { 0x5401e, 0x16 },
373 { 0x5401f, 0x2dd4 },
374 { 0x54020, 0x31 },
375 { 0x54021, 0x4a66 },
376 { 0x54022, 0x4a08 },
377 { 0x54024, 0x16 },
378 { 0x5402b, 0x1000 },
379 { 0x5402c, CH2_LPDDR4_CS },
380 { 0x54032, 0xd400 },
381 { 0x54033, 0x312d },
382 { 0x54034, 0x6600 },
383 { 0x54035, 0x084a },
384 { 0x54036, 0x4a },
385 { 0x54037, 0x1600 },
386 { 0x54038, 0xd400 },
387 { 0x54039, 0x312d },
388 { 0x5403a, 0x6600 },
389 { 0x5403b, 0x084a },
390 { 0x5403c, 0x4a },
391 { 0x5403d, 0x1600 },
392 { 0xd0000, 1 },
393};
394
395/* DRAM PHY init engine image */
396static struct dram_cfg_param lpddr4_phy_pie[] = {
397 { 0xd0000, 0 },
398 { 0x90000, 0x10 },
399 { 0x90001, 0x0400 },
400 { 0x90002, 0x010e },
401 { 0x90003, 0 },
402 { 0x90004, 0 },
403 { 0x90005, 8 },
404 { 0x90029, 0x0b },
405 { 0x9002a, 0x0480 },
406 { 0x9002b, 0x0109 },
407 { 0x9002c, 8 },
408 { 0x9002d, 0x0448 },
409 { 0x9002e, 0x0139 },
410 { 0x9002f, 8 },
411 { 0x90030, 0x0478 },
412 { 0x90031, 0x0109 },
413 { 0x90032, 0 },
414 { 0x90033, 0xe8 },
415 { 0x90034, 0x0109 },
416 { 0x90035, 2 },
417 { 0x90036, 0x10 },
418 { 0x90037, 0x0139 },
419 { 0x90038, 0x0f },
420 { 0x90039, 0x07c0 },
421 { 0x9003a, 0x0139 },
422 { 0x9003b, 0x44 },
423 { 0x9003c, 0x0630 },
424 { 0x9003d, 0x0159 },
425 { 0x9003e, 0x014f },
426 { 0x9003f, 0x0630 },
427 { 0x90040, 0x0159 },
428 { 0x90041, 0x47 },
429 { 0x90042, 0x0630 },
430 { 0x90043, 0x0149 },
431 { 0x90044, 0x4f },
432 { 0x90045, 0x0630 },
433 { 0x90046, 0x0179 },
434 { 0x90047, 8 },
435 { 0x90048, 0xe0 },
436 { 0x90049, 0x0109 },
437 { 0x9004a, 0 },
438 { 0x9004b, 0x07c8 },
439 { 0x9004c, 0x0109 },
440 { 0x9004d, 0 },
441 { 0x9004e, 1 },
442 { 0x9004f, 8 },
443 { 0x90050, 0 },
444 { 0x90051, 0x045a },
445 { 0x90052, 9 },
446 { 0x90053, 0 },
447 { 0x90054, 0x0448 },
448 { 0x90055, 0x0109 },
449 { 0x90056, 0x40 },
450 { 0x90057, 0x0630 },
451 { 0x90058, 0x0179 },
452 { 0x90059, 1 },
453 { 0x9005a, 0x0618 },
454 { 0x9005b, 0x0109 },
455 { 0x9005c, 0x40c0 },
456 { 0x9005d, 0x0630 },
457 { 0x9005e, 0x0149 },
458 { 0x9005f, 8 },
459 { 0x90060, 4 },
460 { 0x90061, 0x48 },
461 { 0x90062, 0x4040 },
462 { 0x90063, 0x0630 },
463 { 0x90064, 0x0149 },
464 { 0x90065, 0 },
465 { 0x90066, 4 },
466 { 0x90067, 0x48 },
467 { 0x90068, 0x40 },
468 { 0x90069, 0x0630 },
469 { 0x9006a, 0x0149 },
470 { 0x9006b, 0x10 },
471 { 0x9006c, 4 },
472 { 0x9006d, 0x18 },
473 { 0x9006e, 0 },
474 { 0x9006f, 4 },
475 { 0x90070, 0x78 },
476 { 0x90071, 0x0549 },
477 { 0x90072, 0x0630 },
478 { 0x90073, 0x0159 },
479 { 0x90074, 0x0d49 },
480 { 0x90075, 0x0630 },
481 { 0x90076, 0x0159 },
482 { 0x90077, 0x094a },
483 { 0x90078, 0x0630 },
484 { 0x90079, 0x0159 },
485 { 0x9007a, 0x0441 },
486 { 0x9007b, 0x0630 },
487 { 0x9007c, 0x0149 },
488 { 0x9007d, 0x42 },
489 { 0x9007e, 0x0630 },
490 { 0x9007f, 0x0149 },
491 { 0x90080, 1 },
492 { 0x90081, 0x0630 },
493 { 0x90082, 0x0149 },
494 { 0x90083, 0 },
495 { 0x90084, 0xe0 },
496 { 0x90085, 0x0109 },
497 { 0x90086, 0x0a },
498 { 0x90087, 0x10 },
499 { 0x90088, 0x0109 },
500 { 0x90089, 9 },
501 { 0x9008a, 0x03c0 },
502 { 0x9008b, 0x0149 },
503 { 0x9008c, 9 },
504 { 0x9008d, 0x03c0 },
505 { 0x9008e, 0x0159 },
506 { 0x9008f, 0x18 },
507 { 0x90090, 0x10 },
508 { 0x90091, 0x0109 },
509 { 0x90092, 0 },
510 { 0x90093, 0x03c0 },
511 { 0x90094, 0x0109 },
512 { 0x90095, 0x18 },
513 { 0x90096, 4 },
514 { 0x90097, 0x48 },
515 { 0x90098, 0x18 },
516 { 0x90099, 4 },
517 { 0x9009a, 0x58 },
518 { 0x9009b, 0x0a },
519 { 0x9009c, 0x10 },
520 { 0x9009d, 0x0109 },
521 { 0x9009e, 2 },
522 { 0x9009f, 0x10 },
523 { 0x900a0, 0x0109 },
524 { 0x900a1, 5 },
525 { 0x900a2, 0x07c0 },
526 { 0x900a3, 0x0109 },
527 { 0x900a4, 0x10 },
528 { 0x900a5, 0x10 },
529 { 0x900a6, 0x0109 },
530 { 0x40000, 0x0811 },
531 { 0x40020, 0x0880 },
532 { 0x40040, 0 },
533 { 0x40060, 0 },
534 { 0x40001, 0x4008 },
535 { 0x40021, 0x83 },
536 { 0x40041, 0x4f },
537 { 0x40061, 0 },
538 { 0x40002, 0x4040 },
539 { 0x40022, 0x83 },
540 { 0x40042, 0x51 },
541 { 0x40062, 0 },
542 { 0x40003, 0x0811 },
543 { 0x40023, 0x0880 },
544 { 0x40043, 0 },
545 { 0x40063, 0 },
546 { 0x40004, 0x0720 },
547 { 0x40024, 0x0f },
548 { 0x40044, 0x1740 },
549 { 0x40064, 0 },
550 { 0x40005, 0x16 },
551 { 0x40025, 0x83 },
552 { 0x40045, 0x4b },
553 { 0x40065, 0 },
554 { 0x40006, 0x0716 },
555 { 0x40026, 0x0f },
556 { 0x40046, 0x2001 },
557 { 0x40066, 0 },
558 { 0x40007, 0x0716 },
559 { 0x40027, 0x0f },
560 { 0x40047, 0x2800 },
561 { 0x40067, 0 },
562 { 0x40008, 0x0716 },
563 { 0x40028, 0x0f },
564 { 0x40048, 0x0f00 },
565 { 0x40068, 0 },
566 { 0x40009, 0x0720 },
567 { 0x40029, 0x0f },
568 { 0x40049, 0x1400 },
569 { 0x40069, 0 },
570 { 0x4000a, 0x0e08 },
571 { 0x4002a, 0x0c15 },
572 { 0x4004a, 0 },
573 { 0x4006a, 0 },
574 { 0x4000b, 0x0623 },
575 { 0x4002b, 0x15 },
576 { 0x4004b, 0 },
577 { 0x4006b, 0 },
578 { 0x4000c, 0x4028 },
579 { 0x4002c, 0x80 },
580 { 0x4004c, 0 },
581 { 0x4006c, 0 },
582 { 0x4000d, 0x0e08 },
583 { 0x4002d, 0x0c1a },
584 { 0x4004d, 0 },
585 { 0x4006d, 0 },
586 { 0x4000e, 0x0623 },
587 { 0x4002e, 0x1a },
588 { 0x4004e, 0 },
589 { 0x4006e, 0 },
590 { 0x4000f, 0x4040 },
591 { 0x4002f, 0x80 },
592 { 0x4004f, 0 },
593 { 0x4006f, 0 },
594 { 0x40010, 0x2604 },
595 { 0x40030, 0x15 },
596 { 0x40050, 0 },
597 { 0x40070, 0 },
598 { 0x40011, 0x0708 },
599 { 0x40031, 5 },
600 { 0x40051, 0 },
601 { 0x40071, 0x2002 },
602 { 0x40012, 8 },
603 { 0x40032, 0x80 },
604 { 0x40052, 0 },
605 { 0x40072, 0 },
606 { 0x40013, 0x2604 },
607 { 0x40033, 0x1a },
608 { 0x40053, 0 },
609 { 0x40073, 0 },
610 { 0x40014, 0x0708 },
611 { 0x40034, 0x0a },
612 { 0x40054, 0 },
613 { 0x40074, 0x2002 },
614 { 0x40015, 0x4040 },
615 { 0x40035, 0x80 },
616 { 0x40055, 0 },
617 { 0x40075, 0 },
618 { 0x40016, 0x060a },
619 { 0x40036, 0x15 },
620 { 0x40056, 0x1200 },
621 { 0x40076, 0 },
622 { 0x40017, 0x061a },
623 { 0x40037, 0x15 },
624 { 0x40057, 0x1300 },
625 { 0x40077, 0 },
626 { 0x40018, 0x060a },
627 { 0x40038, 0x1a },
628 { 0x40058, 0x1200 },
629 { 0x40078, 0 },
630 { 0x40019, 0x0642 },
631 { 0x40039, 0x1a },
632 { 0x40059, 0x1300 },
633 { 0x40079, 0 },
634 { 0x4001a, 0x4808 },
635 { 0x4003a, 0x0880 },
636 { 0x4005a, 0 },
637 { 0x4007a, 0 },
638 { 0x900a7, 0 },
639 { 0x900a8, 0x0790 },
640 { 0x900a9, 0x011a },
641 { 0x900aa, 8 },
642 { 0x900ab, 0x07aa },
643 { 0x900ac, 0x2a },
644 { 0x900ad, 0x10 },
645 { 0x900ae, 0x07b2 },
646 { 0x900af, 0x2a },
647 { 0x900b0, 0 },
648 { 0x900b1, 0x07c8 },
649 { 0x900b2, 0x0109 },
650 { 0x900b3, 0x10 },
651 { 0x900b4, 0x02a8 },
652 { 0x900b5, 0x0129 },
653 { 0x900b6, 8 },
654 { 0x900b7, 0x0370 },
655 { 0x900b8, 0x0129 },
656 { 0x900b9, 0x0a },
657 { 0x900ba, 0x03c8 },
658 { 0x900bb, 0x01a9 },
659 { 0x900bc, 0x0c },
660 { 0x900bd, 0x0408 },
661 { 0x900be, 0x0199 },
662 { 0x900bf, 0x14 },
663 { 0x900c0, 0x0790 },
664 { 0x900c1, 0x011a },
665 { 0x900c2, 8 },
666 { 0x900c3, 4 },
667 { 0x900c4, 0x18 },
668 { 0x900c5, 0x0e },
669 { 0x900c6, 0x0408 },
670 { 0x900c7, 0x0199 },
671 { 0x900c8, 8 },
672 { 0x900c9, 0x8568 },
673 { 0x900ca, 0x0108 },
674 { 0x900cb, 0x18 },
675 { 0x900cc, 0x0790 },
676 { 0x900cd, 0x016a },
677 { 0x900ce, 8 },
678 { 0x900cf, 0x01d8 },
679 { 0x900d0, 0x0169 },
680 { 0x900d1, 0x10 },
681 { 0x900d2, 0x8558 },
682 { 0x900d3, 0x0168 },
683 { 0x900d4, 0x70 },
684 { 0x900d5, 0x0788 },
685 { 0x900d6, 0x016a },
686 { 0x900d7, 0x1ff8 },
687 { 0x900d8, 0x85a8 },
688 { 0x900d9, 0x01e8 },
689 { 0x900da, 0x50 },
690 { 0x900db, 0x0798 },
691 { 0x900dc, 0x016a },
692 { 0x900dd, 0x60 },
693 { 0x900de, 0x07a0 },
694 { 0x900df, 0x016a },
695 { 0x900e0, 8 },
696 { 0x900e1, 0x8310 },
697 { 0x900e2, 0x0168 },
698 { 0x900e3, 8 },
699 { 0x900e4, 0xa310 },
700 { 0x900e5, 0x0168 },
701 { 0x900e6, 0x0a },
702 { 0x900e7, 0x0408 },
703 { 0x900e8, 0x0169 },
704 { 0x900e9, 0x6e },
705 { 0x900ea, 0 },
706 { 0x900eb, 0x68 },
707 { 0x900ec, 0 },
708 { 0x900ed, 0x0408 },
709 { 0x900ee, 0x0169 },
710 { 0x900ef, 0 },
711 { 0x900f0, 0x8310 },
712 { 0x900f1, 0x0168 },
713 { 0x900f2, 0 },
714 { 0x900f3, 0xa310 },
715 { 0x900f4, 0x0168 },
716 { 0x900f5, 0x1ff8 },
717 { 0x900f6, 0x85a8 },
718 { 0x900f7, 0x01e8 },
719 { 0x900f8, 0x68 },
720 { 0x900f9, 0x0798 },
721 { 0x900fa, 0x016a },
722 { 0x900fb, 0x78 },
723 { 0x900fc, 0x07a0 },
724 { 0x900fd, 0x016a },
725 { 0x900fe, 0x68 },
726 { 0x900ff, 0x0790 },
727 { 0x90100, 0x016a },
728 { 0x90101, 8 },
729 { 0x90102, 0x8b10 },
730 { 0x90103, 0x0168 },
731 { 0x90104, 8 },
732 { 0x90105, 0xab10 },
733 { 0x90106, 0x0168 },
734 { 0x90107, 0x0a },
735 { 0x90108, 0x0408 },
736 { 0x90109, 0x0169 },
737 { 0x9010a, 0x58 },
738 { 0x9010b, 0 },
739 { 0x9010c, 0x68 },
740 { 0x9010d, 0 },
741 { 0x9010e, 0x0408 },
742 { 0x9010f, 0x0169 },
743 { 0x90110, 0 },
744 { 0x90111, 0x8b10 },
745 { 0x90112, 0x0168 },
746 { 0x90113, 0 },
747 { 0x90114, 0xab10 },
748 { 0x90115, 0x0168 },
749 { 0x90116, 0 },
750 { 0x90117, 0x01d8 },
751 { 0x90118, 0x0169 },
752 { 0x90119, 0x80 },
753 { 0x9011a, 0x0790 },
754 { 0x9011b, 0x016a },
755 { 0x9011c, 0x18 },
756 { 0x9011d, 0x07aa },
757 { 0x9011e, 0x6a },
758 { 0x9011f, 0x0a },
759 { 0x90120, 0 },
760 { 0x90121, 0x01e9 },
761 { 0x90122, 8 },
762 { 0x90123, 0x8080 },
763 { 0x90124, 0x0108 },
764 { 0x90125, 0x0f },
765 { 0x90126, 0x0408 },
766 { 0x90127, 0x0169 },
767 { 0x90128, 0x0c },
768 { 0x90129, 0 },
769 { 0x9012a, 0x68 },
770 { 0x9012b, 9 },
771 { 0x9012c, 0 },
772 { 0x9012d, 0x01a9 },
773 { 0x9012e, 0 },
774 { 0x9012f, 0x0408 },
775 { 0x90130, 0x0169 },
776 { 0x90131, 0 },
777 { 0x90132, 0x8080 },
778 { 0x90133, 0x0108 },
779 { 0x90134, 8 },
780 { 0x90135, 0x07aa },
781 { 0x90136, 0x6a },
782 { 0x90137, 0 },
783 { 0x90138, 0x8568 },
784 { 0x90139, 0x0108 },
785 { 0x9013a, 0xb7 },
786 { 0x9013b, 0x0790 },
787 { 0x9013c, 0x016a },
788 { 0x9013d, 0x1f },
789 { 0x9013e, 0 },
790 { 0x9013f, 0x68 },
791 { 0x90140, 8 },
792 { 0x90141, 0x8558 },
793 { 0x90142, 0x0168 },
794 { 0x90143, 0x0f },
795 { 0x90144, 0x0408 },
796 { 0x90145, 0x0169 },
797 { 0x90146, 0x0c },
798 { 0x90147, 0 },
799 { 0x90148, 0x68 },
800 { 0x90149, 0 },
801 { 0x9014a, 0x0408 },
802 { 0x9014b, 0x0169 },
803 { 0x9014c, 0 },
804 { 0x9014d, 0x8558 },
805 { 0x9014e, 0x0168 },
806 { 0x9014f, 8 },
807 { 0x90150, 0x03c8 },
808 { 0x90151, 0x01a9 },
809 { 0x90152, 3 },
810 { 0x90153, 0x0370 },
811 { 0x90154, 0x0129 },
812 { 0x90155, 0x20 },
813 { 0x90156, 0x02aa },
814 { 0x90157, 9 },
815 { 0x90158, 0 },
816 { 0x90159, 0x0400 },
817 { 0x9015a, 0x010e },
818 { 0x9015b, 8 },
819 { 0x9015c, 0xe8 },
820 { 0x9015d, 0x0109 },
821 { 0x9015e, 0 },
822 { 0x9015f, 0x8140 },
823 { 0x90160, 0x010c },
824 { 0x90161, 0x10 },
825 { 0x90162, 0x8138 },
826 { 0x90163, 0x010c },
827 { 0x90164, 8 },
828 { 0x90165, 0x07c8 },
829 { 0x90166, 0x0101 },
830 { 0x90167, 8 },
831 { 0x90168, 0 },
832 { 0x90169, 8 },
833 { 0x9016a, 8 },
834 { 0x9016b, 0x0448 },
835 { 0x9016c, 0x0109 },
836 { 0x9016d, 0x0f },
837 { 0x9016e, 0x07c0 },
838 { 0x9016f, 0x0109 },
839 { 0x90170, 0 },
840 { 0x90171, 0xe8 },
841 { 0x90172, 0x0109 },
842 { 0x90173, 0x47 },
843 { 0x90174, 0x0630 },
844 { 0x90175, 0x0109 },
845 { 0x90176, 8 },
846 { 0x90177, 0x0618 },
847 { 0x90178, 0x0109 },
848 { 0x90179, 8 },
849 { 0x9017a, 0xe0 },
850 { 0x9017b, 0x0109 },
851 { 0x9017c, 0 },
852 { 0x9017d, 0x07c8 },
853 { 0x9017e, 0x0109 },
854 { 0x9017f, 8 },
855 { 0x90180, 0x8140 },
856 { 0x90181, 0x010c },
857 { 0x90182, 0 },
858 { 0x90183, 1 },
859 { 0x90184, 8 },
860 { 0x90185, 8 },
861 { 0x90186, 4 },
862 { 0x90187, 8 },
863 { 0x90188, 8 },
864 { 0x90189, 0x07c8 },
865 { 0x9018a, 0x0101 },
866 { 0x90006, 0 },
867 { 0x90007, 0 },
868 { 0x90008, 8 },
869 { 0x90009, 0 },
870 { 0x9000a, 0 },
871 { 0x9000b, 0 },
872 { 0xd00e7, 0x0400 },
873 { 0x90017, 0 },
874 { 0x9001f, 0x2a },
875 { 0x90026, 0x6a },
876 { 0x400d0, 0 },
877 { 0x400d1, 0x0101 },
878 { 0x400d2, 0x0105 },
879 { 0x400d3, 0x0107 },
880 { 0x400d4, 0x010f },
881 { 0x400d5, 0x0202 },
882 { 0x400d6, 0x020a },
883 { 0x400d7, 0x020b },
884 { 0x2003a, 2 },
885 { 0x2000b, 0x64 },
886 { 0x2000c, 0xc8 },
887 { 0x2000d, 0x07d0 },
888 { 0x2000e, 0x2c },
889 { 0x12000b, 0x14 },
890 { 0x12000c, 0x29 },
891 { 0x12000d, 0x01a1 },
892 { 0x12000e, 0x10 },
893 { 0x9000c, 0 },
894 { 0x9000d, 0x0173 },
895 { 0x9000e, 0x60 },
896 { 0x9000f, 0x6110 },
897 { 0x90010, 0x2152 },
898 { 0x90011, 0xdfbd },
899 { 0x90012, 0x60 },
900 { 0x90013, 0x6152 },
901 { 0x20010, 0x5a },
902 { 0x20011, 3 },
903 { 0x40080, 0xe0 },
904 { 0x40081, 0x12 },
905 { 0x40082, 0xe0 },
906 { 0x40083, 0x12 },
907 { 0x40084, 0xe0 },
908 { 0x40085, 0x12 },
909 { 0x140080, 0xe0 },
910 { 0x140081, 0x12 },
911 { 0x140082, 0xe0 },
912 { 0x140083, 0x12 },
913 { 0x140084, 0xe0 },
914 { 0x140085, 0x12 },
915 { 0x400fd, 0x0f },
916 { 0x10011, 1 },
917 { 0x10012, 1 },
918 { 0x10013, 0x0180 },
919 { 0x10018, 1 },
920 { 0x10002, 0x6209 },
921 { 0x100b2, 1 },
922 { 0x101b4, 1 },
923 { 0x102b4, 1 },
924 { 0x103b4, 1 },
925 { 0x104b4, 1 },
926 { 0x105b4, 1 },
927 { 0x106b4, 1 },
928 { 0x107b4, 1 },
929 { 0x108b4, 1 },
930 { 0x11011, 1 },
931 { 0x11012, 1 },
932 { 0x11013, 0x0180 },
933 { 0x11018, 1 },
934 { 0x11002, 0x6209 },
935 { 0x110b2, 1 },
936 { 0x111b4, 1 },
937 { 0x112b4, 1 },
938 { 0x113b4, 1 },
939 { 0x114b4, 1 },
940 { 0x115b4, 1 },
941 { 0x116b4, 1 },
942 { 0x117b4, 1 },
943 { 0x118b4, 1 },
944 { 0x12011, 1 },
945 { 0x12012, 1 },
946 { 0x12013, 0x0180 },
947 { 0x12018, 1 },
948 { 0x12002, 0x6209 },
949 { 0x120b2, 1 },
950 { 0x121b4, 1 },
951 { 0x122b4, 1 },
952 { 0x123b4, 1 },
953 { 0x124b4, 1 },
954 { 0x125b4, 1 },
955 { 0x126b4, 1 },
956 { 0x127b4, 1 },
957 { 0x128b4, 1 },
958 { 0x13011, 1 },
959 { 0x13012, 1 },
960 { 0x13013, 0x0180 },
961 { 0x13018, 1 },
962 { 0x13002, 0x6209 },
963 { 0x130b2, 1 },
964 { 0x131b4, 1 },
965 { 0x132b4, 1 },
966 { 0x133b4, 1 },
967 { 0x134b4, 1 },
968 { 0x135b4, 1 },
969 { 0x136b4, 1 },
970 { 0x137b4, 1 },
971 { 0x138b4, 1 },
972 { 0x2003a, 2 },
973 { 0xc0080, 2 },
974 { 0xd0000, 1 }
975};
976
977static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
978 {
979 /* P0 3200mts 1D */
980 .drate = 3200,
981 .fw_type = FW_1D_IMAGE,
982 .fsp_cfg = lpddr4_fsp0_cfg,
983 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
984 },
985 {
986 /* P1 667mts 1D */
987 .drate = 667,
988 .fw_type = FW_1D_IMAGE,
989 .fsp_cfg = lpddr4_fsp1_cfg,
990 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
991 },
992 {
993 /* P0 3200mts 2D */
994 .drate = 3200,
995 .fw_type = FW_2D_IMAGE,
996 .fsp_cfg = lpddr4_fsp0_2d_cfg,
997 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
998 },
999};
1000
1001/* ddr timing config params */
1002struct dram_timing_info dram_timing_ch2 = {
1003 .ddrc_cfg = lpddr4_ddrc_cfg,
1004 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1005 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1006 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1007 .fsp_msg = lpddr4_dram_fsp_msg,
1008 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1009 .ddrphy_pie = lpddr4_phy_pie,
1010 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
1011 .fsp_table = { 3200, 667, },
1012};