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git01.mediatek.com / filogic / uboot / df41fc634d9e2e7899dc1023a7390708e6d8b886 / . / dts / upstream / src / powerpc / kmeter1.dts
blob: 154f5d293fd3b37718cf3a7ecd3887531c325084 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Keymile KMETER1 Device Tree Source
4 *
5 * 2008-2011 DENX Software Engineering GmbH
6 */
7
8/dts-v1/;
9
10/ {
11 model = "KMETER1";
12 compatible = "keymile,KMETER1";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 aliases {
17 ethernet0 = &enet_piggy2;
18 ethernet1 = &enet_estar1;
19 ethernet2 = &enet_estar2;
20 ethernet3 = &enet_eth1;
21 ethernet4 = &enet_eth2;
22 ethernet5 = &enet_eth3;
23 ethernet6 = &enet_eth4;
24 serial0 = &serial0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8360@0 {
32 device_type = "cpu";
33 reg = <0x0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
37 i-cache-size = <32768>; // L1, 32K
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 bus-frequency = <0>; /* Filled in by U-Boot */
40 clock-frequency = <0>; /* Filled in by U-Boot */
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0 0>; /* Filled in by U-Boot */
47 };
48
49 soc8360@e0000000 {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 device_type = "soc";
53 compatible = "fsl,mpc8360-immr", "simple-bus";
54 ranges = <0x0 0xe0000000 0x00200000>;
55 reg = <0xe0000000 0x00000200>;
56 bus-frequency = <0>; /* Filled in by U-Boot */
57
58 pmc: power@b00 {
59 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
60 reg = <0xb00 0x100 0xa00 0x100>;
61 interrupts = <80 0x8>;
62 interrupt-parent = <&ipic>;
63 };
64
65 i2c@3000 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 cell-index = <0>;
69 compatible = "fsl,mpc8313-i2c","fsl-i2c";
70 reg = <0x3000 0x100>;
71 interrupts = <14 0x8>;
72 interrupt-parent = <&ipic>;
73 clock-frequency = <400000>;
74 };
75
76 serial0: serial@4500 {
77 cell-index = <0>;
78 device_type = "serial";
79 compatible = "fsl,ns16550", "ns16550";
80 reg = <0x4500 0x100>;
81 clock-frequency = <264000000>;
82 interrupts = <9 0x8>;
83 interrupt-parent = <&ipic>;
84 };
85
86 dma@82a8 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
90 reg = <0x82a8 4>;
91 ranges = <0 0x8100 0x1a8>;
92 interrupt-parent = <&ipic>;
93 interrupts = <71 8>;
94 cell-index = <0>;
95 dma-channel@0 {
96 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
97 reg = <0 0x80>;
98 interrupt-parent = <&ipic>;
99 interrupts = <71 8>;
100 };
101 dma-channel@80 {
102 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
103 reg = <0x80 0x80>;
104 interrupt-parent = <&ipic>;
105 interrupts = <71 8>;
106 };
107 dma-channel@100 {
108 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
109 reg = <0x100 0x80>;
110 interrupt-parent = <&ipic>;
111 interrupts = <71 8>;
112 };
113 dma-channel@180 {
114 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
115 reg = <0x180 0x28>;
116 interrupt-parent = <&ipic>;
117 interrupts = <71 8>;
118 };
119 };
120
121 ipic: pic@700 {
122 #address-cells = <0>;
123 #interrupt-cells = <2>;
124 compatible = "fsl,pq2pro-pic", "fsl,ipic";
125 interrupt-controller;
126 reg = <0x700 0x100>;
127 };
128
129 par_io@1400 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <0x1400 0x100>;
133 compatible = "fsl,mpc8360-par_io";
134 num-ports = <7>;
135
136 qe_pio_c: gpio-controller@30 {
137 #gpio-cells = <2>;
138 compatible = "fsl,mpc8360-qe-pario-bank",
139 "fsl,mpc8323-qe-pario-bank";
140 reg = <0x1430 0x18>;
141 gpio-controller;
142 };
143 pio_ucc1: ucc_pin@0 {
144 reg = <0>;
145
146 pio-map = <
147 /* port pin dir open_drain assignment has_irq */
148 0 1 3 0 2 0 /* MDIO */
149 0 2 1 0 1 0 /* MDC */
150
151 0 3 1 0 1 0 /* TxD0 */
152 0 4 1 0 1 0 /* TxD1 */
153 0 5 1 0 1 0 /* TxD2 */
154 0 6 1 0 1 0 /* TxD3 */
155 0 9 2 0 1 0 /* RxD0 */
156 0 10 2 0 1 0 /* RxD1 */
157 0 11 2 0 1 0 /* RxD2 */
158 0 12 2 0 1 0 /* RxD3 */
159 0 7 1 0 1 0 /* TX_EN */
160 0 8 1 0 1 0 /* TX_ER */
161 0 15 2 0 1 0 /* RX_DV */
162 0 16 2 0 1 0 /* RX_ER */
163 0 0 2 0 1 0 /* RX_CLK */
164 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
165 2 8 2 0 1 0 /* GTX125 - CLK9 */
166 >;
167 };
168
169 pio_ucc2: ucc_pin@1 {
170 reg = <1>;
171
172 pio-map = <
173 /* port pin dir open_drain assignment has_irq */
174 0 1 3 0 2 0 /* MDIO */
175 0 2 1 0 1 0 /* MDC */
176
177 0 17 1 0 1 0 /* TxD0 */
178 0 18 1 0 1 0 /* TxD1 */
179 0 19 1 0 1 0 /* TxD2 */
180 0 20 1 0 1 0 /* TxD3 */
181 0 23 2 0 1 0 /* RxD0 */
182 0 24 2 0 1 0 /* RxD1 */
183 0 25 2 0 1 0 /* RxD2 */
184 0 26 2 0 1 0 /* RxD3 */
185 0 21 1 0 1 0 /* TX_EN */
186 0 22 1 0 1 0 /* TX_ER */
187 0 29 2 0 1 0 /* RX_DV */
188 0 30 2 0 1 0 /* RX_ER */
189 0 31 2 0 1 0 /* RX_CLK */
190 2 2 1 0 2 0 /* GTX_CLK - CLK3 */
191 2 3 2 0 1 0 /* GTX125 - CLK4 */
192 >;
193 };
194
195 pio_ucc4: ucc_pin@3 {
196 reg = <3>;
197
198 pio-map = <
199 /* port pin dir open_drain assignment has_irq */
200 0 1 3 0 2 0 /* MDIO */
201 0 2 1 0 1 0 /* MDC */
202
203 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
204 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
205 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
206 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
207 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
208 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
209 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
210
211 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
212 >;
213 };
214
215 pio_ucc5: ucc_pin@4 {
216 reg = <4>;
217
218 pio-map = <
219 /* port pin dir open_drain assignment has_irq */
220 0 1 3 0 2 0 /* MDIO */
221 0 2 1 0 1 0 /* MDC */
222
223 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
224 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
225 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
226 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
227 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
228 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
229 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
230 >;
231 };
232
233 pio_ucc6: ucc_pin@5 {
234 reg = <5>;
235
236 pio-map = <
237 /* port pin dir open_drain assignment has_irq */
238 0 1 3 0 2 0 /* MDIO */
239 0 2 1 0 1 0 /* MDC */
240
241 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
242 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
243 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
244 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
245 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
246 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
247 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
248 >;
249 };
250
251 pio_ucc7: ucc_pin@6 {
252 reg = <6>;
253
254 pio-map = <
255 /* port pin dir open_drain assignment has_irq */
256 0 1 3 0 2 0 /* MDIO */
257 0 2 1 0 1 0 /* MDC */
258
259 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
260 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
261 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
262 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
263 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
264 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
265 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
266 >;
267 };
268
269 pio_ucc8: ucc_pin@7 {
270 reg = <7>;
271
272 pio-map = <
273 /* port pin dir open_drain assignment has_irq */
274 0 1 3 0 2 0 /* MDIO */
275 0 2 1 0 1 0 /* MDC */
276
277 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
278 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
279 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
280 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
281 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
282 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
283 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
284
285 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
286 >;
287 };
288
289 };
290
291 qe@100000 {
292 #address-cells = <1>;
293 #size-cells = <1>;
294 compatible = "fsl,qe";
295 ranges = <0x0 0x100000 0x100000>;
296 reg = <0x100000 0x480>;
297 clock-frequency = <0>; /* Filled in by U-Boot */
298 brg-frequency = <0>; /* Filled in by U-Boot */
299 bus-frequency = <0>; /* Filled in by U-Boot */
300
301 muram@10000 {
302 #address-cells = <1>;
303 #size-cells = <1>;
304 compatible = "fsl,qe-muram", "fsl,cpm-muram";
305 ranges = <0x0 0x00010000 0x0000c000>;
306
307 data-only@0 {
308 compatible = "fsl,qe-muram-data",
309 "fsl,cpm-muram-data";
310 reg = <0x0 0xc000>;
311 };
312 };
313
314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
315 enet_estar1: ucc@2000 {
316 device_type = "network";
317 compatible = "ucc_geth";
318 cell-index = <1>;
319 reg = <0x2000 0x200>;
320 interrupts = <32>;
321 interrupt-parent = <&qeic>;
322 local-mac-address = [ 00 00 00 00 00 00 ];
323 rx-clock-name = "none";
324 tx-clock-name = "clk9";
325 phy-handle = <&phy_estar1>;
326 phy-connection-type = "rgmii-id";
327 pio-handle = <&pio_ucc1>;
328 };
329
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
331 enet_estar2: ucc@3000 {
332 device_type = "network";
333 compatible = "ucc_geth";
334 cell-index = <2>;
335 reg = <0x3000 0x200>;
336 interrupts = <33>;
337 interrupt-parent = <&qeic>;
338 local-mac-address = [ 00 00 00 00 00 00 ];
339 rx-clock-name = "none";
340 tx-clock-name = "clk4";
341 phy-handle = <&phy_estar2>;
342 phy-connection-type = "rgmii-id";
343 pio-handle = <&pio_ucc2>;
344 };
345
346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
347 enet_piggy2: ucc@3200 {
348 device_type = "network";
349 compatible = "ucc_geth";
350 cell-index = <4>;
351 reg = <0x3200 0x200>;
352 interrupts = <35>;
353 interrupt-parent = <&qeic>;
354 local-mac-address = [ 00 00 00 00 00 00 ];
355 rx-clock-name = "none";
356 tx-clock-name = "clk17";
357 phy-handle = <&phy_piggy2>;
358 phy-connection-type = "rmii";
359 pio-handle = <&pio_ucc4>;
360 };
361
362 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
363 enet_eth1: ucc@2400 {
364 device_type = "network";
365 compatible = "ucc_geth";
366 cell-index = <5>;
367 reg = <0x2400 0x200>;
368 interrupts = <40>;
369 interrupt-parent = <&qeic>;
370 local-mac-address = [ 00 00 00 00 00 00 ];
371 rx-clock-name = "none";
372 tx-clock-name = "clk16";
373 phy-handle = <&phy_eth1>;
374 phy-connection-type = "rmii";
375 pio-handle = <&pio_ucc5>;
376 };
377
378 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
379 enet_eth2: ucc@3400 {
380 device_type = "network";
381 compatible = "ucc_geth";
382 cell-index = <6>;
383 reg = <0x3400 0x200>;
384 interrupts = <41>;
385 interrupt-parent = <&qeic>;
386 local-mac-address = [ 00 00 00 00 00 00 ];
387 rx-clock-name = "none";
388 tx-clock-name = "clk16";
389 phy-handle = <&phy_eth2>;
390 phy-connection-type = "rmii";
391 pio-handle = <&pio_ucc6>;
392 };
393
394 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
395 enet_eth3: ucc@2600 {
396 device_type = "network";
397 compatible = "ucc_geth";
398 cell-index = <7>;
399 reg = <0x2600 0x200>;
400 interrupts = <42>;
401 interrupt-parent = <&qeic>;
402 local-mac-address = [ 00 00 00 00 00 00 ];
403 rx-clock-name = "none";
404 tx-clock-name = "clk16";
405 phy-handle = <&phy_eth3>;
406 phy-connection-type = "rmii";
407 pio-handle = <&pio_ucc7>;
408 };
409
410 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
411 enet_eth4: ucc@3600 {
412 device_type = "network";
413 compatible = "ucc_geth";
414 cell-index = <8>;
415 reg = <0x3600 0x200>;
416 interrupts = <43>;
417 interrupt-parent = <&qeic>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 rx-clock-name = "none";
420 tx-clock-name = "clk16";
421 phy-handle = <&phy_eth4>;
422 phy-connection-type = "rmii";
423 pio-handle = <&pio_ucc8>;
424 };
425
426 mdio@3320 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 reg = <0x3320 0x18>;
430 compatible = "fsl,ucc-mdio";
431
432 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
433 phy_piggy2: ethernet-phy@0 {
434 reg = <0x0>;
435 };
436
437 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
438 phy_eth1: ethernet-phy@8 {
439 reg = <0x08>;
440 };
441
442 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
443 phy_eth2: ethernet-phy@9 {
444 reg = <0x09>;
445 };
446
447 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
448 phy_eth3: ethernet-phy@a {
449 reg = <0x0a>;
450 };
451
452 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
453 phy_eth4: ethernet-phy@b {
454 reg = <0x0b>;
455 };
456
457 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
458 phy_estar1: ethernet-phy@10 {
459 interrupt-parent = <&ipic>;
460 interrupts = <17 0x8>;
461 reg = <0x10>;
462 };
463
464 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
465 phy_estar2: ethernet-phy@11 {
466 interrupt-parent = <&ipic>;
467 interrupts = <18 0x8>;
468 reg = <0x11>;
469 };
470 };
471
472 qeic: interrupt-controller@80 {
473 interrupt-controller;
474 compatible = "fsl,qe-ic";
475 #address-cells = <0>;
476 #interrupt-cells = <1>;
477 reg = <0x80 0x80>;
478 big-endian;
479 interrupts = <
480 32 0x8
481 33 0x8
482 34 0x8
483 35 0x8
484 40 0x8
485 41 0x8
486 42 0x8
487 43 0x8
488 >;
489 interrupt-parent = <&ipic>;
490 };
491 };
492 };
493
494 localbus@e0005000 {
495 #address-cells = <2>;
496 #size-cells = <1>;
497 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
498 "simple-bus";
499 reg = <0xe0005000 0xd8>;
500 ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
501 1 0 0xe8000000 0x01000000 /* LB 1 */
502 3 0 0xa0000000 0x10000000>; /* LB 3 */
503
504 flash@0,0 {
505 compatible = "cfi-flash";
506 reg = <0 0 0x04000000>;
507 #address-cells = <1>;
508 #size-cells = <1>;
509 bank-width = <2>;
510 partition@0 { /* 768KB */
511 label = "u-boot";
512 reg = <0 0xC0000>;
513 };
514 partition@c0000 { /* 128KB */
515 label = "env";
516 reg = <0xC0000 0x20000>;
517 };
518 partition@e0000 { /* 128KB */
519 label = "envred";
520 reg = <0xE0000 0x20000>;
521 };
522 partition@100000 { /* 64512KB */
523 label = "ubi0";
524 reg = <0x100000 0x3F00000>;
525 };
526 };
527 };
528};