| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) |
| 4 | */ |
| 5 | /dts-v1/; |
| 6 | |
| 7 | /include/ "skeleton_hs_idu.dtsi" |
| 8 | |
| 9 | / { |
| 10 | model = "snps,zebu_hs-smp"; |
| 11 | compatible = "snps,zebu_hs"; |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; |
| 14 | interrupt-parent = <&core_intc>; |
| 15 | |
| 16 | memory { |
| 17 | device_type = "memory"; |
| 18 | reg = <0x80000000 0x20000000>; /* 512 */ |
| 19 | }; |
| 20 | |
| 21 | chosen { |
| 22 | bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; |
| 23 | }; |
| 24 | |
| 25 | aliases { |
| 26 | serial0 = &uart0; |
| 27 | }; |
| 28 | |
| 29 | fpga { |
| 30 | compatible = "simple-bus"; |
| 31 | #address-cells = <1>; |
| 32 | #size-cells = <1>; |
| 33 | |
| 34 | /* child and parent address space 1:1 mapped */ |
| 35 | ranges; |
| 36 | |
| 37 | core_clk: core_clk { |
| 38 | #clock-cells = <0>; |
| 39 | compatible = "fixed-clock"; |
| 40 | clock-frequency = <50000000>; /* 50 MHZ */ |
| 41 | }; |
| 42 | |
| 43 | core_intc: interrupt-controller { |
| 44 | compatible = "snps,archs-intc"; |
| 45 | interrupt-controller; |
| 46 | #interrupt-cells = <1>; |
| 47 | }; |
| 48 | |
| 49 | idu_intc: idu-interrupt-controller { |
| 50 | compatible = "snps,archs-idu-intc"; |
| 51 | interrupt-controller; |
| 52 | interrupt-parent = <&core_intc>; |
| 53 | #interrupt-cells = <1>; |
| 54 | }; |
| 55 | |
| 56 | uart0: serial@f0000000 { |
| 57 | compatible = "ns16550a"; |
| 58 | reg = <0xf0000000 0x2000>; |
| 59 | interrupt-parent = <&idu_intc>; |
| 60 | interrupts = <0>; |
| 61 | clock-frequency = <50000000>; |
| 62 | baud = <115200>; |
| 63 | reg-shift = <2>; |
| 64 | reg-io-width = <4>; |
| 65 | no-loopback-test = <1>; |
| 66 | }; |
| 67 | |
| 68 | arcpct0: pct { |
| 69 | compatible = "snps,archs-pct"; |
| 70 | #interrupt-cells = <1>; |
| 71 | interrupts = <20>; |
| 72 | }; |
| 73 | }; |
| 74 | }; |