| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/watchdog/ti,rti-wdt.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Texas Instruments K3 SoC Watchdog Timer |
| 8 | |
| 9 | maintainers: |
| 10 | - Tero Kristo <t-kristo@ti.com> |
| 11 | |
| 12 | description: |
| 13 | The TI K3 SoC watchdog timer is implemented via the RTI (Real Time |
| 14 | Interrupt) IP module. This timer adds a support for windowed watchdog |
| 15 | mode, which will signal an error if it is pinged outside the watchdog |
| 16 | time window, meaning either too early or too late. The error signal |
| 17 | generated can be routed to either interrupt a safety controller or |
| 18 | to directly reset the SoC. |
| 19 | |
| 20 | allOf: |
| 21 | - $ref: watchdog.yaml# |
| 22 | |
| 23 | properties: |
| 24 | compatible: |
| 25 | enum: |
| 26 | - ti,j7-rti-wdt |
| 27 | |
| 28 | reg: |
| 29 | maxItems: 1 |
| 30 | |
| 31 | clocks: |
| 32 | maxItems: 1 |
| 33 | |
| 34 | power-domains: |
| 35 | maxItems: 1 |
| 36 | |
| 37 | memory-region: |
| 38 | maxItems: 1 |
| 39 | description: |
| 40 | Contains the watchdog reserved memory. It is optional. |
| 41 | In the reserved memory, the specified values, which are |
| 42 | PON_REASON_SOF_NUM(0xBBBBCCCC), PON_REASON_MAGIC_NUM(0xDDDDDDDD), |
| 43 | and PON_REASON_EOF_NUM(0xCCCCBBBB), are pre-stored at the first |
| 44 | 3 * 4 bytes to tell that last boot was caused by watchdog reset. |
| 45 | Once the PON reason is captured by driver(rti_wdt.c), the driver |
| 46 | is supposed to wipe the whole memory region. Surely, if this |
| 47 | property is set, at least 12 bytes reserved memory starting from |
| 48 | specific memory address(0xa220000) should be set. More please |
| 49 | refer to example. |
| 50 | |
| 51 | required: |
| 52 | - compatible |
| 53 | - reg |
| 54 | - clocks |
| 55 | - power-domains |
| 56 | |
| 57 | unevaluatedProperties: false |
| 58 | |
| 59 | examples: |
| 60 | - | |
| 61 | /* |
| 62 | * RTI WDT in main domain on J721e SoC. Assigned clocks are used to |
| 63 | * select the source clock for the watchdog, forcing it to tick with |
| 64 | * a 32kHz clock in this case. Add a reserved memory(optional) to keep |
| 65 | * the watchdog reset cause persistent, which was be written in 12 bytes |
| 66 | * starting from 0xa2200000 by RTI Watchdog Firmware, then make it |
| 67 | * possible to get watchdog reset cause in driver. |
| 68 | * |
| 69 | * Reserved memory should be defined as follows: |
| 70 | * reserved-memory { |
| 71 | * wdt_reset_memory_region: wdt-memory@a2200000 { |
| 72 | * reg = <0x00 0xa2200000 0x00 0x1000>; |
| 73 | * no-map; |
| 74 | * }; |
| 75 | * } |
| 76 | */ |
| 77 | #include <dt-bindings/soc/ti,sci_pm_domain.h> |
| 78 | |
| 79 | watchdog@2200000 { |
| 80 | compatible = "ti,j7-rti-wdt"; |
| 81 | reg = <0x2200000 0x100>; |
| 82 | clocks = <&k3_clks 252 1>; |
| 83 | power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; |
| 84 | assigned-clocks = <&k3_clks 252 1>; |
| 85 | assigned-clock-parents = <&k3_clks 252 5>; |
| 86 | memory-region = <&wdt_reset_memory_region>; |
| 87 | }; |