blob: 32fd535a514ad1cb7e9ed55c595224835161579a [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Universal Flash Storage (UFS) Controller
8
9maintainers:
10 - Stanley Chu <stanley.chu@mediatek.com>
11
12allOf:
13 - $ref: ufs-common.yaml
14
15properties:
16 compatible:
17 enum:
18 - mediatek,mt8183-ufshci
19 - mediatek,mt8192-ufshci
20
21 clocks:
22 maxItems: 1
23
24 clock-names:
25 items:
26 - const: ufs
27
28 phys:
29 maxItems: 1
30
31 reg:
32 maxItems: 1
33
34 vcc-supply: true
35
36required:
37 - compatible
38 - clocks
39 - clock-names
40 - phys
41 - reg
42 - vcc-supply
43
44unevaluatedProperties: false
45
46examples:
47 - |
48 #include <dt-bindings/clock/mt8183-clk.h>
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50
51 soc {
52 #address-cells = <2>;
53 #size-cells = <2>;
54
55 ufs@ff3c0000 {
56 compatible = "mediatek,mt8183-ufshci";
57 reg = <0 0x11270000 0 0x2300>;
58 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
59 phys = <&ufsphy>;
60
61 clocks = <&infracfg_ao CLK_INFRA_UFS>;
62 clock-names = "ufs";
63 freq-table-hz = <0 0>;
64
65 vcc-supply = <&mt_pmic_vemc_ldo_reg>;
66 };
67 };