| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm MSM SoC Serial UART |
| 8 | |
| 9 | maintainers: |
| 10 | - Bjorn Andersson <andersson@kernel.org> |
| 11 | - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
| 12 | |
| 13 | description: |
| 14 | The MSM serial UART hardware is designed for low-speed use cases where a |
| 15 | dma-engine isn't needed. From a software perspective it's mostly compatible |
| 16 | with the MSM serial UARTDM except that it only supports reading and writing |
| 17 | one character at a time. |
| 18 | |
| 19 | properties: |
| 20 | compatible: |
| 21 | const: qcom,msm-uart |
| 22 | |
| 23 | clocks: |
| 24 | maxItems: 1 |
| 25 | |
| 26 | clock-names: |
| 27 | items: |
| 28 | - const: core |
| 29 | |
| 30 | interrupts: |
| 31 | maxItems: 1 |
| 32 | |
| 33 | reg: |
| 34 | maxItems: 1 |
| 35 | |
| 36 | required: |
| 37 | - compatible |
| 38 | - clock-names |
| 39 | - clocks |
| 40 | - interrupts |
| 41 | - reg |
| 42 | |
| 43 | allOf: |
| 44 | - $ref: /schemas/serial/serial.yaml# |
| 45 | |
| 46 | unevaluatedProperties: false |
| 47 | |
| 48 | examples: |
| 49 | - | |
| 50 | serial@a9c00000 { |
| 51 | compatible = "qcom,msm-uart"; |
| 52 | reg = <0xa9c00000 0x1000>; |
| 53 | interrupts = <11>; |
| 54 | clocks = <&uart_cxc>; |
| 55 | clock-names = "core"; |
| 56 | }; |