| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Zynq UltraScale+ MPSoC and Versal reset |
| 8 | |
| 9 | maintainers: |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 10 | - Mubin Sayyed <mubin.sayyed@amd.com> |
| 11 | - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 12 | |
| 13 | description: | |
| 14 | The Zynq UltraScale+ MPSoC and Versal has several different resets. |
| 15 | |
| 16 | The PS reset subsystem is responsible for handling the external reset |
| 17 | input to the device and that all internal reset requirements are met |
| 18 | for the system (as a whole) and for the functional units. |
| 19 | |
| 20 | Please also refer to reset.txt in this directory for common reset |
| 21 | controller binding usage. Device nodes that need access to reset |
| 22 | lines should specify them as a reset phandle in their corresponding |
| 23 | node as specified in reset.txt. |
| 24 | |
| 25 | For list of all valid reset indices for Zynq UltraScale+ MPSoC |
| 26 | <dt-bindings/reset/xlnx-zynqmp-resets.h> |
| 27 | |
| 28 | For list of all valid reset indices for Versal |
| 29 | <dt-bindings/reset/xlnx-versal-resets.h> |
| 30 | |
| 31 | properties: |
| 32 | compatible: |
| 33 | enum: |
| 34 | - xlnx,zynqmp-reset |
| 35 | - xlnx,versal-reset |
| 36 | - xlnx,versal-net-reset |
| 37 | |
| 38 | "#reset-cells": |
| 39 | const: 1 |
| 40 | |
| 41 | required: |
| 42 | - compatible |
| 43 | - "#reset-cells" |
| 44 | |
| 45 | additionalProperties: false |
| 46 | |
| 47 | examples: |
| 48 | - | |
| 49 | zynqmp_reset: reset-controller { |
| 50 | compatible = "xlnx,zynqmp-reset"; |
| 51 | #reset-cells = <1>; |
| 52 | }; |
| 53 | |
| 54 | ... |