Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: TI K3 DSP devices |
| 8 | |
| 9 | maintainers: |
| 10 | - Suman Anna <s-anna@ti.com> |
| 11 | |
| 12 | description: | |
| 13 | The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems |
| 14 | that are used to offload some of the processor-intensive tasks or algorithms, |
| 15 | for achieving various system level goals. |
| 16 | |
| 17 | These processor sub-systems usually contain additional sub-modules like |
| 18 | L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory |
| 19 | controller, a dedicated local power/sleep controller etc. The DSP processor |
| 20 | cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a |
| 21 | TMS320C71x CorePac processor. |
| 22 | |
| 23 | Each DSP Core sub-system is represented as a single DT node. Each node has a |
| 24 | number of required or optional properties that enable the OS running on the |
| 25 | host processor (Arm CorePac) to perform the device management of the remote |
| 26 | processor and to communicate with the remote processor. |
| 27 | |
| 28 | allOf: |
| 29 | - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# |
| 30 | |
| 31 | properties: |
| 32 | compatible: |
| 33 | enum: |
| 34 | - ti,am62a-c7xv-dsp |
| 35 | - ti,j721e-c66-dsp |
| 36 | - ti,j721e-c71-dsp |
| 37 | - ti,j721s2-c71-dsp |
| 38 | description: |
| 39 | Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs |
| 40 | Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs |
| 41 | Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs |
| 42 | Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs |
| 43 | |
| 44 | resets: |
| 45 | description: | |
| 46 | Should contain the phandle to the reset controller node managing the |
| 47 | local resets for this device, and a reset specifier. |
| 48 | maxItems: 1 |
| 49 | |
| 50 | firmware-name: |
| 51 | description: | |
| 52 | Should contain the name of the default firmware image |
| 53 | file located on the firmware search path |
| 54 | |
| 55 | mboxes: |
| 56 | description: | |
| 57 | OMAP Mailbox specifier denoting the sub-mailbox, to be used for |
| 58 | communication with the remote processor. This property should match |
| 59 | with the sub-mailbox node used in the firmware image. |
| 60 | maxItems: 1 |
| 61 | |
| 62 | memory-region: |
| 63 | minItems: 2 |
| 64 | maxItems: 8 |
| 65 | description: | |
| 66 | phandle to the reserved memory nodes to be associated with the remoteproc |
| 67 | device. There should be at least two reserved memory nodes defined. The |
| 68 | reserved memory nodes should be carveout nodes, and should be defined as |
| 69 | per the bindings in |
| 70 | Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt |
| 71 | items: |
| 72 | - description: region used for dynamic DMA allocations like vrings and |
| 73 | vring buffers |
| 74 | - description: region reserved for firmware image sections |
| 75 | additionalItems: true |
| 76 | |
| 77 | # Optional properties: |
| 78 | # -------------------- |
| 79 | |
| 80 | sram: |
| 81 | $ref: /schemas/types.yaml#/definitions/phandle-array |
| 82 | minItems: 1 |
| 83 | maxItems: 4 |
| 84 | items: |
| 85 | maxItems: 1 |
| 86 | description: | |
| 87 | phandles to one or more reserved on-chip SRAM regions. The regions |
| 88 | should be defined as child nodes of the respective SRAM node, and |
| 89 | should be defined as per the generic bindings in, |
| 90 | Documentation/devicetree/bindings/sram/sram.yaml |
| 91 | |
| 92 | if: |
| 93 | properties: |
| 94 | compatible: |
| 95 | enum: |
| 96 | - ti,j721e-c66-dsp |
| 97 | then: |
| 98 | properties: |
| 99 | reg: |
| 100 | items: |
| 101 | - description: Address and Size of the L2 SRAM internal memory region |
| 102 | - description: Address and Size of the L1 PRAM internal memory region |
| 103 | - description: Address and Size of the L1 DRAM internal memory region |
| 104 | reg-names: |
| 105 | items: |
| 106 | - const: l2sram |
| 107 | - const: l1pram |
| 108 | - const: l1dram |
| 109 | else: |
| 110 | if: |
| 111 | properties: |
| 112 | compatible: |
| 113 | enum: |
| 114 | - ti,am62a-c7xv-dsp |
| 115 | - ti,j721e-c71-dsp |
| 116 | - ti,j721s2-c71-dsp |
| 117 | then: |
| 118 | properties: |
| 119 | reg: |
| 120 | items: |
| 121 | - description: Address and Size of the L2 SRAM internal memory region |
| 122 | - description: Address and Size of the L1 DRAM internal memory region |
| 123 | reg-names: |
| 124 | items: |
| 125 | - const: l2sram |
| 126 | - const: l1dram |
| 127 | |
| 128 | required: |
| 129 | - compatible |
| 130 | - reg |
| 131 | - reg-names |
| 132 | - ti,sci |
| 133 | - ti,sci-dev-id |
| 134 | - ti,sci-proc-ids |
| 135 | - resets |
| 136 | - firmware-name |
| 137 | - mboxes |
| 138 | - memory-region |
| 139 | |
| 140 | unevaluatedProperties: false |
| 141 | |
| 142 | examples: |
| 143 | - | |
| 144 | soc { |
| 145 | #address-cells = <2>; |
| 146 | #size-cells = <2>; |
| 147 | |
| 148 | mailbox0_cluster3: mailbox-0 { |
| 149 | #mbox-cells = <1>; |
| 150 | }; |
| 151 | |
| 152 | mailbox0_cluster4: mailbox-1 { |
| 153 | #mbox-cells = <1>; |
| 154 | }; |
| 155 | |
| 156 | bus@100000 { |
| 157 | compatible = "simple-bus"; |
| 158 | #address-cells = <2>; |
| 159 | #size-cells = <2>; |
| 160 | ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ |
| 161 | <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */ |
| 162 | <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ |
| 163 | <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */ |
| 164 | |
| 165 | /* J721E C66_0 DSP node */ |
| 166 | dsp@4d80800000 { |
| 167 | compatible = "ti,j721e-c66-dsp"; |
| 168 | reg = <0x4d 0x80800000 0x00 0x00048000>, |
| 169 | <0x4d 0x80e00000 0x00 0x00008000>, |
| 170 | <0x4d 0x80f00000 0x00 0x00008000>; |
| 171 | reg-names = "l2sram", "l1pram", "l1dram"; |
| 172 | ti,sci = <&dmsc>; |
| 173 | ti,sci-dev-id = <142>; |
| 174 | ti,sci-proc-ids = <0x03 0xFF>; |
| 175 | resets = <&k3_reset 142 1>; |
| 176 | firmware-name = "j7-c66_0-fw"; |
| 177 | memory-region = <&c66_0_dma_memory_region>, |
| 178 | <&c66_0_memory_region>; |
| 179 | mboxes = <&mailbox0_cluster3 &mbox_c66_0>; |
| 180 | }; |
| 181 | |
| 182 | /* J721E C71_0 DSP node */ |
| 183 | c71_0: dsp@64800000 { |
| 184 | compatible = "ti,j721e-c71-dsp"; |
| 185 | reg = <0x00 0x64800000 0x00 0x00080000>, |
| 186 | <0x00 0x64e00000 0x00 0x0000c000>; |
| 187 | reg-names = "l2sram", "l1dram"; |
| 188 | ti,sci = <&dmsc>; |
| 189 | ti,sci-dev-id = <15>; |
| 190 | ti,sci-proc-ids = <0x30 0xFF>; |
| 191 | resets = <&k3_reset 15 1>; |
| 192 | firmware-name = "j7-c71_0-fw"; |
| 193 | memory-region = <&c71_0_dma_memory_region>, |
| 194 | <&c71_0_memory_region>; |
| 195 | mboxes = <&mailbox0_cluster4 &mbox_c71_0>; |
| 196 | }; |
| 197 | }; |
| 198 | }; |