| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * Marvell Armada 375 SoC pinctrl driver for mpp |
| 2 | |
| 3 | Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding |
| 4 | part and usage. |
| 5 | |
| 6 | Required properties: |
| 7 | - compatible: "marvell,88f6720-pinctrl" |
| 8 | - reg: register specifier of MPP registers |
| 9 | |
| 10 | Available mpp pins/groups and functions: |
| 11 | Note: brackets (x) are not part of the mpp name for marvell,function and given |
| 12 | only for more detailed description in this document. |
| 13 | |
| 14 | name pins functions |
| 15 | ================================================================================ |
| 16 | mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) |
| 17 | mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) |
| 18 | mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) |
| 19 | mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) |
| 20 | mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) |
| 21 | mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) |
| 22 | mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk) |
| 23 | mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) |
| 24 | mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) |
| 25 | mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) |
| 26 | mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) |
| 27 | mpp11 11 gpio, dev(a0), led(c2), audio(sdo) |
| 28 | mpp12 12 gpio, dev(a1), audio(bclk) |
| 29 | mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout) |
| 30 | mpp14 14 gpio, i2c0(sda), uart1(txd) |
| 31 | mpp15 15 gpio, i2c0(sck), uart1(rxd) |
| 32 | mpp16 16 gpio, uart0(txd) |
| 33 | mpp17 17 gpio, uart0(rxd) |
| 34 | mpp18 18 gpio, tdm(int) |
| 35 | mpp19 19 gpio, tdm(rst) |
| 36 | mpp20 20 gpio, tdm(pclk) |
| 37 | mpp21 21 gpio, tdm(fsync) |
| 38 | mpp22 22 gpio, tdm(drx) |
| 39 | mpp23 23 gpio, tdm(dtx) |
| 40 | mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts) |
| 41 | mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts) |
| 42 | mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts) |
| 43 | mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts) |
| 44 | mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) |
| 45 | mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) |
| 46 | mpp30 30 gpio, ge1(txd0), spi1(cs0) |
| 47 | mpp31 31 gpio, ge1(txd1), spi1(mosi) |
| 48 | mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig) |
| 49 | mpp33 33 gpio, ge1(txd3), spi1(miso) |
| 50 | mpp34 34 gpio, ge1(txclkout), spi1(sck) |
| 51 | mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) |
| 52 | mpp36 36 gpio, pcie0(clkreq) |
| 53 | mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc) |
| 54 | mpp38 38 gpio, pcie1(clkreq), ge(mdio) |
| 55 | mpp39 39 gpio, ref(clkout) |
| 56 | mpp40 40 gpio, uart1(txd) |
| 57 | mpp41 41 gpio, uart1(rxd) |
| 58 | mpp42 42 gpio, spi1(cs2), led(c0) |
| 59 | mpp43 43 gpio, sata0(prsnt), dram(vttctrl) |
| 60 | mpp44 44 gpio, sata0(prsnt) |
| 61 | mpp45 45 gpio, spi0(cs2), pcie0(rstout) |
| 62 | mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) |
| 63 | mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) |
| 64 | mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) |
| 65 | mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) |
| 66 | mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) |
| 67 | mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) |
| 68 | mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) |
| 69 | mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3) |
| 70 | mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl) |
| 71 | mpp55 55 gpio, ge0(rxclk), ge1(rxclk) |
| 72 | mpp56 56 gpio, ge0(txclkout), ge1(txclkout) |
| 73 | mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) |
| 74 | mpp58 58 gpio, led(c0) |
| 75 | mpp59 59 gpio, led(c1) |
| 76 | mpp60 60 gpio, uart1(txd), led(c2) |
| 77 | mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) |
| 78 | mpp62 62 gpio, i2c1(sck), led(p1) |
| 79 | mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last) |
| 80 | mpp64 64 gpio, dram(vttctrl), led(p3) |
| 81 | mpp65 65 gpio, sata1(prsnt) |
| 82 | mpp66 66 gpio, ptp(evreq), spi1(cs3) |