blob: 1074310a8e7a2cb6ba9fabdabc61a634234cb29f [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -06001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm X1E80100 PCI Express Root Complex
8
9maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description:
14 Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
15 the Synopsys DesignWare PCIe IP.
16
17properties:
18 compatible:
19 const: qcom,pcie-x1e80100
20
21 reg:
22 minItems: 5
23 maxItems: 6
24
25 reg-names:
26 minItems: 5
27 items:
28 - const: parf # Qualcomm specific registers
29 - const: dbi # DesignWare PCIe registers
30 - const: elbi # External local bus interface registers
31 - const: atu # ATU address space
32 - const: config # PCIe configuration space
33 - const: mhi # MHI registers
34
35 clocks:
36 minItems: 7
37 maxItems: 7
38
39 clock-names:
40 items:
41 - const: aux # Auxiliary clock
42 - const: cfg # Configuration clock
43 - const: bus_master # Master AXI clock
44 - const: bus_slave # Slave AXI clock
45 - const: slave_q2a # Slave Q2A clock
46 - const: noc_aggr # Aggre NoC PCIe AXI clock
47 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
48
49 interrupts:
50 minItems: 8
51 maxItems: 8
52
53 interrupt-names:
54 items:
55 - const: msi0
56 - const: msi1
57 - const: msi2
58 - const: msi3
59 - const: msi4
60 - const: msi5
61 - const: msi6
62 - const: msi7
63
64 resets:
65 minItems: 1
66 maxItems: 2
67
68 reset-names:
69 minItems: 1
70 items:
71 - const: pci # PCIe core reset
72 - const: link_down # PCIe link down reset
73
74allOf:
75 - $ref: qcom,pcie-common.yaml#
76
77unevaluatedProperties: false
78
79examples:
80 - |
81 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
82 #include <dt-bindings/gpio/gpio.h>
83 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
85
86 soc {
87 #address-cells = <2>;
88 #size-cells = <2>;
89
90 pcie@1c08000 {
91 compatible = "qcom,pcie-x1e80100";
92 reg = <0 0x01c08000 0 0x3000>,
93 <0 0x7c000000 0 0xf1d>,
94 <0 0x7c000f40 0 0xa8>,
95 <0 0x7c001000 0 0x1000>,
96 <0 0x7c100000 0 0x100000>,
97 <0 0x01c0b000 0 0x1000>;
98 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
99 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
100 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
101
102 bus-range = <0x00 0xff>;
103 device_type = "pci";
104 linux,pci-domain = <0>;
105 num-lanes = <2>;
106
107 #address-cells = <3>;
108 #size-cells = <2>;
109
110 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
111 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
112 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
113 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
114 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
115 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
116 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
117 clock-names = "aux",
118 "cfg",
119 "bus_master",
120 "bus_slave",
121 "slave_q2a",
122 "noc_aggr",
123 "cnoc_sf_axi";
124
125 dma-coherent;
126
127 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
135 interrupt-names = "msi0", "msi1", "msi2", "msi3",
136 "msi4", "msi5", "msi6", "msi7";
137 #interrupt-cells = <1>;
138 interrupt-map-mask = <0 0 0 0x7>;
139 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
140 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
141 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
142 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
143
144 interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
145 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>;
146 interconnect-names = "pcie-mem", "cpu-pcie";
147
148 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
149 <0x100 &apps_smmu 0x1401 0x1>;
150
151 phys = <&pcie4_phy>;
152 phy-names = "pciephy";
153
154 pinctrl-0 = <&pcie0_default_state>;
155 pinctrl-names = "default";
156
157 power-domains = <&gcc GCC_PCIE_4_GDSC>;
158
159 resets = <&gcc GCC_PCIE_4_BCR>;
160 reset-names = "pci";
161
162 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
163 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
164 };
165 };