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git01.mediatek.com / filogic / uboot / df41fc634d9e2e7899dc1023a7390708e6d8b886 / . / dts / upstream / Bindings / net / qca,ar803x.yaml
blob: 3acd09f0da863137f8a05e435a1fd28a536c2acd [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros AR803x PHY
8
9maintainers:
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
13
14description: |
15 Bindings for Qualcomm Atheros AR803x PHYs
16
17allOf:
18 - $ref: ethernet-phy.yaml#
19
20properties:
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
23 $ref: /schemas/types.yaml#/definitions/uint32
24 enum: [25000000, 50000000, 62500000, 125000000]
25
26 qca,clk-out-strength:
27 description: Clock output driver strength.
28 $ref: /schemas/types.yaml#/definitions/uint32
29 enum: [0, 1, 2]
30
31 qca,disable-smarteee:
32 description: Disable Atheros SmartEEE feature.
33 type: boolean
34
35 qca,keep-pll-enabled:
36 description: |
37 If set, keep the PLL enabled even if there is no link. Useful if you
38 want to use the clock output without an ethernet link.
39
40 Only supported on the AR8031.
41 type: boolean
42
43 qca,disable-hibernation-mode:
44 description: |
45 Disable Atheros AR803X PHYs hibernation mode. If present, indicates
46 that the hardware of PHY will not enter power saving mode when the
47 cable is disconnected. And the RX_CLK always keeps outputting a
48 valid clock.
49 type: boolean
50
51 qca,smarteee-tw-us-100m:
52 description: EEE Tw parameter for 100M links.
53 $ref: /schemas/types.yaml#/definitions/uint32
54 minimum: 1
55 maximum: 255
56
57 qca,smarteee-tw-us-1g:
58 description: EEE Tw parameter for gigabit links.
59 $ref: /schemas/types.yaml#/definitions/uint32
60 minimum: 1
61 maximum: 255
62
63 vddio-supply:
64 description: |
65 RGMII I/O voltage regulator (see regulator/regulator.yaml).
66
67 The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
68 either connect this to the vddio-regulator (1.5V / 1.8V) or the
69 vddh-regulator (2.5V).
70
71 Only supported on the AR8031.
72
73 vddio-regulator:
74 type: object
75 description:
76 Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
77 $ref: /schemas/regulator/regulator.yaml
78 unevaluatedProperties: false
79
80 vddh-regulator:
81 type: object
82 description:
83 Dummy subnode to model the external connection of the PHY VDDH
84 regulator to VDDIO.
85 $ref: /schemas/regulator/regulator.yaml
86 unevaluatedProperties: false
87
88unevaluatedProperties: false
89
90examples:
91 - |
92 #include <dt-bindings/net/qca-ar803x.h>
93
94 ethernet {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 phy-mode = "rgmii-id";
99
100 ethernet-phy@0 {
101 reg = <0>;
102
103 qca,clk-out-frequency = <125000000>;
104 qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
105
106 vddio-supply = <&vddio>;
107
108 vddio: vddio-regulator {
109 regulator-min-microvolt = <1800000>;
110 regulator-max-microvolt = <1800000>;
111 };
112 };
113 };
114 - |
115 #include <dt-bindings/net/qca-ar803x.h>
116
117 ethernet {
118 #address-cells = <1>;
119 #size-cells = <0>;
120
121 phy-mode = "rgmii-id";
122
123 ethernet-phy@0 {
124 reg = <0>;
125
126 qca,clk-out-frequency = <50000000>;
127 qca,keep-pll-enabled;
128
129 vddio-supply = <&vddh>;
130
131 vddh: vddh-regulator {
132 };
133 };
134 };