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git01.mediatek.com / filogic / uboot / df41fc634d9e2e7899dc1023a7390708e6d8b886 / . / dts / upstream / Bindings / net / mediatek,net.yaml
blob: 3202dc7967c5b686d1c74194daca4c315f8d87a7 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
12
13description:
14 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15 have dual GMAC ports.
16
17properties:
18 compatible:
19 enum:
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
25 - mediatek,mt7981-eth
26 - mediatek,mt7986-eth
27 - mediatek,mt7988-eth
28 - ralink,rt5350-eth
29
30 reg:
31 maxItems: 1
32
33 clocks: true
34 clock-names: true
35
36 interrupts:
37 minItems: 1
38 maxItems: 4
39
40 power-domains:
41 maxItems: 1
42
43 resets:
44 maxItems: 3
45
46 reset-names:
47 items:
48 - const: fe
49 - const: gmac
50 - const: ppe
51
52 mediatek,ethsys:
53 $ref: /schemas/types.yaml#/definitions/phandle
54 description:
55 Phandle to the syscon node that handles the port setup.
56
57 cci-control-port: true
58
59 mediatek,hifsys:
60 $ref: /schemas/types.yaml#/definitions/phandle
61 description:
62 Phandle to the mediatek hifsys controller used to provide various clocks
63 and reset to the system.
64
65 mediatek,infracfg:
66 $ref: /schemas/types.yaml#/definitions/phandle
67 description:
68 Phandle to the syscon node that handles the path from GMAC to
69 PHY variants.
70
71 mediatek,sgmiisys:
72 $ref: /schemas/types.yaml#/definitions/phandle-array
73 minItems: 1
74 maxItems: 2
75 items:
76 maxItems: 1
77 description:
78 A list of phandle to the syscon node that handles the SGMII setup which is required for
79 those SoCs equipped with SGMII.
80
81 mediatek,wed:
82 $ref: /schemas/types.yaml#/definitions/phandle-array
83 minItems: 2
84 maxItems: 2
85 items:
86 maxItems: 1
87 description:
88 List of phandles to wireless ethernet dispatch nodes.
89
90 mediatek,wed-pcie:
91 $ref: /schemas/types.yaml#/definitions/phandle
92 description:
93 Phandle to the mediatek wed-pcie controller.
94
95 dma-coherent: true
96
97 mdio-bus:
98 $ref: mdio.yaml#
99 unevaluatedProperties: false
100
101 "#address-cells":
102 const: 1
103
104 "#size-cells":
105 const: 0
106
107allOf:
108 - $ref: ethernet-controller.yaml#
109 - if:
110 properties:
111 compatible:
112 contains:
113 enum:
114 - mediatek,mt2701-eth
115 - mediatek,mt7623-eth
116 then:
117 properties:
118 interrupts:
119 maxItems: 3
120
121 clocks:
122 minItems: 4
123 maxItems: 4
124
125 clock-names:
126 items:
127 - const: ethif
128 - const: esw
129 - const: gp1
130 - const: gp2
131
132 mediatek,infracfg: false
133
134 mediatek,pctl:
135 $ref: /schemas/types.yaml#/definitions/phandle
136 description:
137 Phandle to the syscon node that handles the ports slew rate and
138 driver current.
139
140 mediatek,wed: false
141
142 mediatek,wed-pcie: false
143
144 - if:
145 properties:
146 compatible:
147 contains:
148 enum:
149 - mediatek,mt7621-eth
150 then:
151 properties:
152 interrupts:
153 maxItems: 1
154
155 clocks:
156 minItems: 2
157 maxItems: 2
158
159 clock-names:
160 items:
161 - const: ethif
162 - const: fe
163
164 mediatek,infracfg: false
165
166 mediatek,wed: false
167
168 mediatek,wed-pcie: false
169
170 - if:
171 properties:
172 compatible:
173 contains:
174 const: mediatek,mt7622-eth
175 then:
176 properties:
177 interrupts:
178 maxItems: 3
179
180 clocks:
181 minItems: 11
182 maxItems: 11
183
184 clock-names:
185 items:
186 - const: ethif
187 - const: esw
188 - const: gp0
189 - const: gp1
190 - const: gp2
191 - const: sgmii_tx250m
192 - const: sgmii_rx250m
193 - const: sgmii_cdr_ref
194 - const: sgmii_cdr_fb
195 - const: sgmii_ck
196 - const: eth2pll
197
198 mediatek,infracfg: false
199
200 mediatek,sgmiisys:
201 minItems: 1
202 maxItems: 1
203
204 mediatek,pcie-mirror:
205 $ref: /schemas/types.yaml#/definitions/phandle
206 description:
207 Phandle to the mediatek pcie-mirror controller.
208
209 mediatek,wed-pcie: false
210
211 - if:
212 properties:
213 compatible:
214 contains:
215 const: mediatek,mt7629-eth
216 then:
217 properties:
218 interrupts:
219 maxItems: 3
220
221 clocks:
222 minItems: 17
223 maxItems: 17
224
225 clock-names:
226 items:
227 - const: ethif
228 - const: sgmiitop
229 - const: esw
230 - const: gp0
231 - const: gp1
232 - const: gp2
233 - const: fe
234 - const: sgmii_tx250m
235 - const: sgmii_rx250m
236 - const: sgmii_cdr_ref
237 - const: sgmii_cdr_fb
238 - const: sgmii2_tx250m
239 - const: sgmii2_rx250m
240 - const: sgmii2_cdr_ref
241 - const: sgmii2_cdr_fb
242 - const: sgmii_ck
243 - const: eth2pll
244
245 mediatek,sgmiisys:
246 minItems: 2
247 maxItems: 2
248
249 mediatek,wed: false
250
251 mediatek,wed-pcie: false
252
253 - if:
254 properties:
255 compatible:
256 contains:
257 const: mediatek,mt7981-eth
258 then:
259 properties:
260 interrupts:
261 minItems: 4
262
263 clocks:
264 minItems: 15
265 maxItems: 15
266
267 clock-names:
268 items:
269 - const: fe
270 - const: gp2
271 - const: gp1
272 - const: wocpu0
273 - const: sgmii_ck
274 - const: sgmii_tx250m
275 - const: sgmii_rx250m
276 - const: sgmii_cdr_ref
277 - const: sgmii_cdr_fb
278 - const: sgmii2_tx250m
279 - const: sgmii2_rx250m
280 - const: sgmii2_cdr_ref
281 - const: sgmii2_cdr_fb
282 - const: netsys0
283 - const: netsys1
284
285 mediatek,infracfg: false
286
287 mediatek,sgmiisys:
288 minItems: 2
289 maxItems: 2
290
291 - if:
292 properties:
293 compatible:
294 contains:
295 const: mediatek,mt7986-eth
296 then:
297 properties:
298 interrupts:
299 minItems: 4
300
301 clocks:
302 minItems: 15
303 maxItems: 15
304
305 clock-names:
306 items:
307 - const: fe
308 - const: gp2
309 - const: gp1
310 - const: wocpu1
311 - const: wocpu0
312 - const: sgmii_tx250m
313 - const: sgmii_rx250m
314 - const: sgmii_cdr_ref
315 - const: sgmii_cdr_fb
316 - const: sgmii2_tx250m
317 - const: sgmii2_rx250m
318 - const: sgmii2_cdr_ref
319 - const: sgmii2_cdr_fb
320 - const: netsys0
321 - const: netsys1
322
323 mediatek,infracfg: false
324
325 mediatek,sgmiisys:
326 minItems: 2
327 maxItems: 2
328
329 - if:
330 properties:
331 compatible:
332 contains:
333 const: mediatek,mt7988-eth
334 then:
335 properties:
336 interrupts:
337 minItems: 4
338
339 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]340 minItems: 24
341 maxItems: 24
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]342
343 clock-names:
344 items:
345 - const: crypto
346 - const: fe
347 - const: gp2
348 - const: gp1
349 - const: gp3
350 - const: ethwarp_wocpu2
351 - const: ethwarp_wocpu1
352 - const: ethwarp_wocpu0
353 - const: esw
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]354 - const: top_eth_gmii_sel
355 - const: top_eth_refck_50m_sel
356 - const: top_eth_sys_200m_sel
357 - const: top_eth_sys_sel
358 - const: top_eth_xgmii_sel
359 - const: top_eth_mii_sel
360 - const: top_netsys_sel
361 - const: top_netsys_500m_sel
362 - const: top_netsys_pao_2x_sel
363 - const: top_netsys_sync_250m_sel
364 - const: top_netsys_ppefb_250m_sel
365 - const: top_netsys_warp_sel
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]366 - const: xgp1
367 - const: xgp2
368 - const: xgp3
369
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]370patternProperties:
371 "^mac@[0-1]$":
372 type: object
373 unevaluatedProperties: false
374 allOf:
375 - $ref: ethernet-controller.yaml#
376 description:
377 Ethernet MAC node
378 properties:
379 compatible:
380 const: mediatek,eth-mac
381
382 reg:
383 maxItems: 1
384
385 required:
386 - reg
387 - compatible
388
389required:
390 - compatible
391 - reg
392 - interrupts
393 - clocks
394 - clock-names
395 - mediatek,ethsys
396
397unevaluatedProperties: false
398
399examples:
400 - |
401 #include <dt-bindings/interrupt-controller/arm-gic.h>
402 #include <dt-bindings/interrupt-controller/irq.h>
403 #include <dt-bindings/clock/mt7622-clk.h>
404 #include <dt-bindings/power/mt7622-power.h>
405
406 soc {
407 #address-cells = <2>;
408 #size-cells = <2>;
409
410 ethernet: ethernet@1b100000 {
411 compatible = "mediatek,mt7622-eth";
412 reg = <0 0x1b100000 0 0x20000>;
413 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
414 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
415 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
416 clocks = <&topckgen CLK_TOP_ETH_SEL>,
417 <&ethsys CLK_ETH_ESW_EN>,
418 <&ethsys CLK_ETH_GP0_EN>,
419 <&ethsys CLK_ETH_GP1_EN>,
420 <&ethsys CLK_ETH_GP2_EN>,
421 <&sgmiisys CLK_SGMII_TX250M_EN>,
422 <&sgmiisys CLK_SGMII_RX250M_EN>,
423 <&sgmiisys CLK_SGMII_CDR_REF>,
424 <&sgmiisys CLK_SGMII_CDR_FB>,
425 <&topckgen CLK_TOP_SGMIIPLL>,
426 <&apmixedsys CLK_APMIXED_ETH2PLL>;
427 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
428 "sgmii_tx250m", "sgmii_rx250m",
429 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
430 "eth2pll";
431 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
432 mediatek,ethsys = <&ethsys>;
433 mediatek,sgmiisys = <&sgmiisys>;
434 cci-control-port = <&cci_control2>;
435 mediatek,pcie-mirror = <&pcie_mirror>;
436 mediatek,hifsys = <&hifsys>;
437 dma-coherent;
438
439 #address-cells = <1>;
440 #size-cells = <0>;
441
442 mdio0: mdio-bus {
443 #address-cells = <1>;
444 #size-cells = <0>;
445
446 phy0: ethernet-phy@0 {
447 reg = <0>;
448 };
449
450 phy1: ethernet-phy@1 {
451 reg = <1>;
452 };
453 };
454
455 gmac0: mac@0 {
456 compatible = "mediatek,eth-mac";
457 phy-mode = "rgmii";
458 phy-handle = <&phy0>;
459 reg = <0>;
460 };
461
462 gmac1: mac@1 {
463 compatible = "mediatek,eth-mac";
464 phy-mode = "rgmii";
465 phy-handle = <&phy1>;
466 reg = <1>;
467 };
468 };
469 };
470
471 - |
472 #include <dt-bindings/interrupt-controller/arm-gic.h>
473 #include <dt-bindings/interrupt-controller/irq.h>
474 #include <dt-bindings/clock/mt7622-clk.h>
475
476 soc {
477 #address-cells = <2>;
478 #size-cells = <2>;
479
480 eth: ethernet@15100000 {
481 #define CLK_ETH_FE_EN 0
482 #define CLK_ETH_WOCPU1_EN 3
483 #define CLK_ETH_WOCPU0_EN 4
484 #define CLK_TOP_NETSYS_SEL 43
485 #define CLK_TOP_NETSYS_500M_SEL 44
486 #define CLK_TOP_NETSYS_2X_SEL 46
487 #define CLK_TOP_SGM_325M_SEL 47
488 #define CLK_APMIXED_NET2PLL 1
489 #define CLK_APMIXED_SGMPLL 3
490
491 compatible = "mediatek,mt7986-eth";
492 reg = <0 0x15100000 0 0x80000>;
493 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&ethsys CLK_ETH_FE_EN>,
498 <&ethsys CLK_ETH_GP2_EN>,
499 <&ethsys CLK_ETH_GP1_EN>,
500 <&ethsys CLK_ETH_WOCPU1_EN>,
501 <&ethsys CLK_ETH_WOCPU0_EN>,
502 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
503 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
504 <&sgmiisys0 CLK_SGMII_CDR_REF>,
505 <&sgmiisys0 CLK_SGMII_CDR_FB>,
506 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
507 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
508 <&sgmiisys1 CLK_SGMII_CDR_REF>,
509 <&sgmiisys1 CLK_SGMII_CDR_FB>,
510 <&topckgen CLK_TOP_NETSYS_SEL>,
511 <&topckgen CLK_TOP_NETSYS_SEL>;
512 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
513 "sgmii_tx250m", "sgmii_rx250m",
514 "sgmii_cdr_ref", "sgmii_cdr_fb",
515 "sgmii2_tx250m", "sgmii2_rx250m",
516 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
517 "netsys0", "netsys1";
518 mediatek,ethsys = <&ethsys>;
519 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
520 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
521 <&topckgen CLK_TOP_SGM_325M_SEL>;
522 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
523 <&apmixedsys CLK_APMIXED_SGMPLL>;
524
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 mdio: mdio-bus {
529 #address-cells = <1>;
530 #size-cells = <0>;
531
532 phy5: ethernet-phy@0 {
533 compatible = "ethernet-phy-id67c9.de0a";
534 phy-mode = "2500base-x";
535 reset-gpios = <&pio 6 1>;
536 reset-deassert-us = <20000>;
537 reg = <5>;
538 };
539
540 phy6: ethernet-phy@1 {
541 compatible = "ethernet-phy-id67c9.de0a";
542 phy-mode = "2500base-x";
543 reg = <6>;
544 };
545 };
546
547 mac0: mac@0 {
548 compatible = "mediatek,eth-mac";
549 phy-mode = "2500base-x";
550 phy-handle = <&phy5>;
551 reg = <0>;
552 };
553
554 mac1: mac@1 {
555 compatible = "mediatek,eth-mac";
556 phy-mode = "2500base-x";
557 phy-handle = <&phy6>;
558 reg = <1>;
559 };
560 };
561 };