Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/net/fsl,fec.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Freescale Fast Ethernet Controller (FEC) |
| 8 | |
| 9 | maintainers: |
| 10 | - Shawn Guo <shawnguo@kernel.org> |
| 11 | - Wei Fang <wei.fang@nxp.com> |
| 12 | - NXP Linux Team <linux-imx@nxp.com> |
| 13 | |
| 14 | allOf: |
| 15 | - $ref: ethernet-controller.yaml# |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | oneOf: |
| 20 | - enum: |
| 21 | - fsl,imx25-fec |
| 22 | - fsl,imx27-fec |
| 23 | - fsl,imx28-fec |
| 24 | - fsl,imx6q-fec |
| 25 | - fsl,mvf600-fec |
| 26 | - fsl,s32v234-fec |
| 27 | - items: |
| 28 | - enum: |
| 29 | - fsl,imx53-fec |
| 30 | - fsl,imx6sl-fec |
| 31 | - const: fsl,imx25-fec |
| 32 | - items: |
| 33 | - enum: |
| 34 | - fsl,imx35-fec |
| 35 | - fsl,imx51-fec |
| 36 | - const: fsl,imx27-fec |
| 37 | - items: |
| 38 | - enum: |
| 39 | - fsl,imx6ul-fec |
| 40 | - fsl,imx6sx-fec |
| 41 | - const: fsl,imx6q-fec |
| 42 | - items: |
| 43 | - enum: |
| 44 | - fsl,imx7d-fec |
| 45 | - const: fsl,imx6sx-fec |
| 46 | - items: |
| 47 | - const: fsl,imx8mq-fec |
| 48 | - const: fsl,imx6sx-fec |
| 49 | - items: |
| 50 | - enum: |
| 51 | - fsl,imx8mm-fec |
| 52 | - fsl,imx8mn-fec |
| 53 | - fsl,imx8mp-fec |
| 54 | - fsl,imx93-fec |
| 55 | - const: fsl,imx8mq-fec |
| 56 | - const: fsl,imx6sx-fec |
| 57 | - items: |
| 58 | - const: fsl,imx8qm-fec |
| 59 | - const: fsl,imx6sx-fec |
| 60 | - items: |
| 61 | - enum: |
| 62 | - fsl,imx8dxl-fec |
| 63 | - fsl,imx8qxp-fec |
| 64 | - const: fsl,imx8qm-fec |
| 65 | - const: fsl,imx6sx-fec |
| 66 | - items: |
| 67 | - enum: |
| 68 | - fsl,imx8ulp-fec |
| 69 | - const: fsl,imx6ul-fec |
| 70 | - const: fsl,imx6q-fec |
| 71 | |
| 72 | reg: |
| 73 | maxItems: 1 |
| 74 | |
| 75 | interrupts: |
| 76 | minItems: 1 |
| 77 | maxItems: 4 |
| 78 | |
| 79 | interrupt-names: |
| 80 | oneOf: |
| 81 | - items: |
| 82 | - const: int0 |
| 83 | - items: |
| 84 | - const: int0 |
| 85 | - const: pps |
| 86 | - items: |
| 87 | - const: int0 |
| 88 | - const: int1 |
| 89 | - const: int2 |
| 90 | - items: |
| 91 | - const: int0 |
| 92 | - const: int1 |
| 93 | - const: int2 |
| 94 | - const: pps |
| 95 | |
| 96 | clocks: |
| 97 | minItems: 2 |
| 98 | maxItems: 5 |
| 99 | description: |
| 100 | The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing. |
| 101 | The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock. |
| 102 | The "ptp"(option), for IEEE1588 timer clock that requires the clock. |
| 103 | The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like |
| 104 | RGMII TXC clock or RMII reference clock. It depends on board design, |
| 105 | the clock is required if RGMII TXC and RMII reference clock source from |
| 106 | SOC internal PLL. |
| 107 | The "enet_out"(option), output clock for external device, like supply clock |
| 108 | for PHY. The clock is required if PHY clock source from SOC. |
| 109 | The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz. |
| 110 | The clock is required if SoC RGMII enable clock delay. |
| 111 | |
| 112 | clock-names: |
| 113 | minItems: 2 |
| 114 | maxItems: 5 |
| 115 | items: |
| 116 | enum: |
| 117 | - ipg |
| 118 | - ahb |
| 119 | - ptp |
| 120 | - enet_clk_ref |
| 121 | - enet_out |
| 122 | - enet_2x_txclk |
| 123 | |
| 124 | phy-mode: true |
| 125 | |
| 126 | phy-handle: true |
| 127 | |
| 128 | fixed-link: true |
| 129 | |
| 130 | local-mac-address: true |
| 131 | |
| 132 | mac-address: true |
| 133 | |
| 134 | nvmem-cells: true |
| 135 | |
| 136 | nvmem-cell-names: true |
| 137 | |
| 138 | tx-internal-delay-ps: |
| 139 | enum: [0, 2000] |
| 140 | |
| 141 | rx-internal-delay-ps: |
| 142 | enum: [0, 2000] |
| 143 | |
| 144 | phy-supply: |
| 145 | description: |
| 146 | Regulator that powers the Ethernet PHY. |
| 147 | |
| 148 | power-domains: |
| 149 | maxItems: 1 |
| 150 | |
| 151 | fsl,num-tx-queues: |
| 152 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 153 | description: |
| 154 | The property is valid for enet-avb IP, which supports hw multi queues. |
| 155 | Should specify the tx queue number, otherwise set tx queue number to 1. |
| 156 | enum: [1, 2, 3] |
| 157 | |
| 158 | fsl,num-rx-queues: |
| 159 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 160 | description: |
| 161 | The property is valid for enet-avb IP, which supports hw multi queues. |
| 162 | Should specify the rx queue number, otherwise set rx queue number to 1. |
| 163 | enum: [1, 2, 3] |
| 164 | |
| 165 | fsl,magic-packet: |
| 166 | $ref: /schemas/types.yaml#/definitions/flag |
| 167 | description: |
| 168 | If present, indicates that the hardware supports waking up via magic packet. |
| 169 | |
| 170 | fsl,err006687-workaround-present: |
| 171 | $ref: /schemas/types.yaml#/definitions/flag |
| 172 | description: |
| 173 | If present indicates that the system has the hardware workaround for |
| 174 | ERR006687 applied and does not need a software workaround. |
| 175 | |
| 176 | fsl,stop-mode: |
| 177 | $ref: /schemas/types.yaml#/definitions/phandle-array |
| 178 | items: |
| 179 | - items: |
| 180 | - description: phandle to general purpose register node |
| 181 | - description: the gpr register offset for ENET stop request |
| 182 | - description: the gpr bit offset for ENET stop request |
| 183 | description: |
| 184 | Register bits of stop mode control, the format is <&gpr req_gpr req_bit>. |
| 185 | |
| 186 | mdio: |
| 187 | $ref: mdio.yaml# |
| 188 | unevaluatedProperties: false |
| 189 | description: |
| 190 | Specifies the mdio bus in the FEC, used as a container for phy nodes. |
| 191 | |
| 192 | # Deprecated optional properties: |
| 193 | # To avoid these, create a phy node according to ethernet-phy.yaml in the same |
| 194 | # directory, and point the FEC's "phy-handle" property to it. Then use |
| 195 | # the phy's reset binding, again described by ethernet-phy.yaml. |
| 196 | |
| 197 | phy-reset-gpios: |
| 198 | deprecated: true |
| 199 | description: |
| 200 | Should specify the gpio for phy reset. |
| 201 | |
| 202 | phy-reset-duration: |
| 203 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 204 | deprecated: true |
| 205 | description: |
| 206 | Reset duration in milliseconds. Should present only if property |
| 207 | "phy-reset-gpios" is available. Missing the property will have the |
| 208 | duration be 1 millisecond. Numbers greater than 1000 are invalid |
| 209 | and 1 millisecond will be used instead. |
| 210 | |
| 211 | phy-reset-active-high: |
| 212 | type: boolean |
| 213 | deprecated: true |
| 214 | description: |
| 215 | If present then the reset sequence using the GPIO specified in the |
| 216 | "phy-reset-gpios" property is reversed (H=reset state, L=operation state). |
| 217 | |
| 218 | phy-reset-post-delay: |
| 219 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 220 | deprecated: true |
| 221 | description: |
| 222 | Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay |
| 223 | milliseconds will be observed after the phy-reset-gpios has been toggled. |
| 224 | Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. |
| 225 | Other delays are invalid. |
| 226 | |
Tom Rini | 6bb92fc | 2024-05-20 09:54:58 -0600 | [diff] [blame] | 227 | iommus: |
| 228 | maxItems: 1 |
| 229 | |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 230 | required: |
| 231 | - compatible |
| 232 | - reg |
| 233 | - interrupts |
| 234 | |
| 235 | # FIXME: We had better set additionalProperties to false to avoid invalid or at |
| 236 | # least undocumented properties. However, PHY may have a deprecated option to |
| 237 | # place PHY OF properties in the MAC node, such as Micrel PHY, and we can find |
| 238 | # these boards which is based on i.MX6QDL. |
| 239 | unevaluatedProperties: false |
| 240 | |
| 241 | examples: |
| 242 | - | |
| 243 | ethernet@83fec000 { |
| 244 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
| 245 | reg = <0x83fec000 0x4000>; |
| 246 | interrupts = <87>; |
| 247 | phy-mode = "mii"; |
| 248 | phy-reset-gpios = <&gpio2 14 0>; |
| 249 | phy-supply = <®_fec_supply>; |
| 250 | }; |
| 251 | |
| 252 | ethernet@83fed000 { |
| 253 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
| 254 | reg = <0x83fed000 0x4000>; |
| 255 | interrupts = <87>; |
| 256 | phy-mode = "mii"; |
| 257 | phy-reset-gpios = <&gpio2 14 0>; |
| 258 | phy-supply = <®_fec_supply>; |
| 259 | phy-handle = <ðphy0>; |
| 260 | |
| 261 | mdio { |
| 262 | #address-cells = <1>; |
| 263 | #size-cells = <0>; |
| 264 | |
| 265 | ethphy0: ethernet-phy@0 { |
| 266 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 267 | reg = <0>; |
| 268 | }; |
| 269 | }; |
| 270 | }; |