| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * AMD 10GbE driver (amd-xgbe) |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible: Should be "amd,xgbe-seattle-v1a" |
| 5 | - reg: Address and length of the register sets for the device |
| 6 | - MAC registers |
| 7 | - PCS registers |
| 8 | - SerDes Rx/Tx registers |
| 9 | - SerDes integration registers (1/2) |
| 10 | - SerDes integration registers (2/2) |
| 11 | - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt |
| 12 | listed is required and is the general device interrupt. If the optional |
| 13 | amd,per-channel-interrupt property is specified, then one additional |
| 14 | interrupt for each DMA channel supported by the device should be specified. |
| 15 | The last interrupt listed should be the PCS auto-negotiation interrupt. |
| 16 | - clocks: |
| 17 | - DMA clock for the amd-xgbe device (used for calculating the |
| 18 | correct Rx interrupt watchdog timer value on a DMA channel |
| 19 | for coalescing) |
| 20 | - PTP clock for the amd-xgbe device |
| 21 | - clock-names: Should be the names of the clocks |
| 22 | - "dma_clk" for the DMA clock |
| 23 | - "ptp_clk" for the PTP clock |
| 24 | - phy-mode: See ethernet.txt file in the same directory |
| 25 | |
| 26 | Optional properties: |
| 27 | - dma-coherent: Present if dma operations are coherent |
| 28 | - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate |
| 29 | a unique interrupt for each DMA channel - this requires an additional |
| 30 | interrupt be configured for each DMA channel |
| 31 | - amd,speed-set: Speed capabilities of the device |
| 32 | 0 - 1GbE and 10GbE (default) |
| 33 | 1 - 2.5GbE and 10GbE |
| 34 | |
| 35 | The MAC address will be determined using the optional properties defined in |
| 36 | ethernet.txt. |
| 37 | |
| 38 | The following optional properties are represented by an array with each |
| 39 | value corresponding to a particular speed. The first array value represents |
| 40 | the setting for the 1GbE speed, the second value for the 2.5GbE speed and |
| 41 | the third value for the 10GbE speed. All three values are required if the |
| 42 | property is used. |
| 43 | - amd,serdes-blwc: Baseline wandering correction enablement |
| 44 | 0 - Off |
| 45 | 1 - On |
| 46 | - amd,serdes-cdr-rate: CDR rate speed selection |
| 47 | - amd,serdes-pq-skew: PQ (data sampling) skew |
| 48 | - amd,serdes-tx-amp: TX amplitude boost |
| 49 | - amd,serdes-dfe-tap-config: DFE taps available to run |
| 50 | - amd,serdes-dfe-tap-enable: DFE taps to enable |
| 51 | |
| 52 | Example: |
| 53 | xgbe@e0700000 { |
| 54 | compatible = "amd,xgbe-seattle-v1a"; |
| 55 | reg = <0 0xe0700000 0 0x80000>, |
| 56 | <0 0xe0780000 0 0x80000>, |
| 57 | <0 0xe1240800 0 0x00400>, |
| 58 | <0 0xe1250000 0 0x00060>, |
| 59 | <0 0xe1250080 0 0x00004>; |
| 60 | interrupt-parent = <&gic>; |
| 61 | interrupts = <0 325 4>, |
| 62 | <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, |
| 63 | <0 323 4>; |
| 64 | amd,per-channel-interrupt; |
| 65 | clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; |
| 66 | clock-names = "dma_clk", "ptp_clk"; |
| 67 | phy-mode = "xgmii"; |
| 68 | mac-address = [ 02 a1 a2 a3 a4 a5 ]; |
| 69 | amd,speed-set = <0>; |
| 70 | amd,serdes-blwc = <1>, <1>, <0>; |
| 71 | amd,serdes-cdr-rate = <2>, <2>, <7>; |
| 72 | amd,serdes-pq-skew = <10>, <10>, <30>; |
| 73 | amd,serdes-tx-amp = <15>, <15>, <10>; |
| 74 | amd,serdes-dfe-tap-config = <3>, <3>, <1>; |
| 75 | amd,serdes-dfe-tap-enable = <0>, <0>, <127>; |
| 76 | }; |