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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/adi,adin.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Analog Devices ADIN1200/ADIN1300 PHY
8
9maintainers:
10 - Alexandru Tachici <alexandru.tachici@analog.com>
11
12description: |
13 Bindings for Analog Devices Industrial Ethernet PHYs
14
15allOf:
16 - $ref: ethernet-phy.yaml#
17
18properties:
19 adi,rx-internal-delay-ps:
20 description: |
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
23 enum: [ 1600, 1800, 2000, 2200, 2400 ]
24 default: 2000
25
26 adi,tx-internal-delay-ps:
27 description: |
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
30 enum: [ 1600, 1800, 2000, 2200, 2400 ]
31 default: 2000
32
33 adi,fifo-depth-bits:
34 description: |
35 When operating in RMII mode, this option configures the FIFO depth.
36 enum: [ 4, 8, 12, 16, 20, 24 ]
37 default: 8
38
39 adi,phy-output-clock:
40 description: |
41 Select clock output on GP_CLK pin. Two clocks are available:
42 A 25MHz reference and a free-running 125MHz.
43 The phy can alternatively automatically switch between the reference and
44 the 125MHz clocks based on its internal state.
45 $ref: /schemas/types.yaml#/definitions/string
46 enum:
47 - 25mhz-reference
48 - 125mhz-free-running
49 - adaptive-free-running
50
51 adi,phy-output-reference-clock:
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
53 type: boolean
54
55unevaluatedProperties: false
56
57examples:
58 - |
59 ethernet {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 phy-mode = "rgmii-id";
64
65 ethernet-phy@0 {
66 reg = <0>;
67
68 adi,rx-internal-delay-ps = <1800>;
69 adi,tx-internal-delay-ps = <2200>;
70 };
71 };
72 - |
73 ethernet {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 phy-mode = "rmii";
78
79 ethernet-phy@1 {
80 reg = <1>;
81
82 adi,fifo-depth-bits = <16>;
83 };
84 };