| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 11 | |
| 12 | description: |
| 13 | The Inter-Processor Communication Controller (IPCC) is a centralized hardware |
| 14 | to route interrupts across various subsystems. It involves a three-level |
| 15 | addressing scheme called protocol, client and signal. For example, consider an |
| 16 | entity on the Application Processor Subsystem (APSS) that wants to listen to |
| 17 | Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such |
| 18 | a case, the client would be Modem (client-id is 2) and the signal would be |
| 19 | SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC) |
| 20 | protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h |
| 21 | for the list of such IDs. |
| 22 | |
| 23 | properties: |
| 24 | compatible: |
| 25 | items: |
| 26 | - enum: |
| 27 | - qcom,qdu1000-ipcc |
| 28 | - qcom,sa8775p-ipcc |
| 29 | - qcom,sc7280-ipcc |
| 30 | - qcom,sc8280xp-ipcc |
| 31 | - qcom,sm6350-ipcc |
| 32 | - qcom,sm6375-ipcc |
| 33 | - qcom,sm8250-ipcc |
| 34 | - qcom,sm8350-ipcc |
| 35 | - qcom,sm8450-ipcc |
| 36 | - qcom,sm8550-ipcc |
| 37 | - qcom,sm8650-ipcc |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 38 | - qcom,x1e80100-ipcc |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 39 | - const: qcom,ipcc |
| 40 | |
| 41 | reg: |
| 42 | maxItems: 1 |
| 43 | |
| 44 | interrupts: |
| 45 | maxItems: 1 |
| 46 | |
| 47 | interrupt-controller: true |
| 48 | |
| 49 | "#interrupt-cells": |
| 50 | const: 3 |
| 51 | description: |
| 52 | The first cell is the client-id, the second cell is the signal-id and the |
| 53 | third cell is the interrupt type. |
| 54 | |
| 55 | "#mbox-cells": |
| 56 | const: 2 |
| 57 | description: |
| 58 | The first cell is the client-id, and the second cell is the signal-id. |
| 59 | |
| 60 | required: |
| 61 | - compatible |
| 62 | - reg |
| 63 | - interrupts |
| 64 | - interrupt-controller |
| 65 | - "#interrupt-cells" |
| 66 | - "#mbox-cells" |
| 67 | |
| 68 | additionalProperties: false |
| 69 | |
| 70 | examples: |
| 71 | - | |
| 72 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 73 | #include <dt-bindings/mailbox/qcom-ipcc.h> |
| 74 | |
| 75 | mailbox@408000 { |
| 76 | compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; |
| 77 | reg = <0x408000 0x1000>; |
| 78 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| 79 | interrupt-controller; |
| 80 | #interrupt-cells = <3>; |
| 81 | #mbox-cells = <2>; |
| 82 | }; |